1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __LS1088A_QDS_H 7 #define __LS1088A_QDS_H 8 9 #include "ls1088a_common.h" 10 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_TFABOOT 18 #define CONFIG_SYS_MMC_ENV_DEV 0 19 20 #define CONFIG_ENV_SIZE 0x20000 21 #define CONFIG_ENV_OFFSET 0x500000 22 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 23 CONFIG_ENV_OFFSET) 24 #define CONFIG_ENV_SECT_SIZE 0x40000 25 #else 26 #if defined(CONFIG_QSPI_BOOT) 27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 28 #define CONFIG_ENV_SECT_SIZE 0x40000 29 #elif defined(CONFIG_SD_BOOT) 30 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 31 #define CONFIG_SYS_MMC_ENV_DEV 0 32 #define CONFIG_ENV_SIZE 0x2000 33 #else 34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 35 #define CONFIG_ENV_SECT_SIZE 0x20000 36 #define CONFIG_ENV_SIZE 0x20000 37 #endif 38 #endif 39 40 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 41 #define CONFIG_QIXIS_I2C_ACCESS 42 #define SYS_NO_FLASH 43 44 #undef CONFIG_CMD_IMLS 45 #define CONFIG_SYS_CLK_FREQ 100000000 46 #define CONFIG_DDR_CLK_FREQ 100000000 47 #else 48 #define CONFIG_QIXIS_I2C_ACCESS 49 #define CONFIG_SYS_I2C_EARLY_INIT 50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 51 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 52 #endif 53 54 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 55 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 56 57 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 58 59 #define CONFIG_DDR_SPD 60 #define CONFIG_DDR_ECC 61 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 62 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 63 #define SPD_EEPROM_ADDRESS 0x51 64 #define CONFIG_SYS_SPD_BUS_NUM 0 65 66 67 /* 68 * IFC Definitions 69 */ 70 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 71 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 72 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 73 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 74 75 #define CONFIG_SYS_NOR0_CSPR \ 76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 77 CSPR_PORT_SIZE_16 | \ 78 CSPR_MSEL_NOR | \ 79 CSPR_V) 80 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85 #define CONFIG_SYS_NOR1_CSPR \ 86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 87 CSPR_PORT_SIZE_16 | \ 88 CSPR_MSEL_NOR | \ 89 CSPR_V) 90 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 91 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 92 CSPR_PORT_SIZE_16 | \ 93 CSPR_MSEL_NOR | \ 94 CSPR_V) 95 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 96 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 97 FTIM0_NOR_TEADC(0x5) | \ 98 FTIM0_NOR_TAVDS(0x6) | \ 99 FTIM0_NOR_TEAHC(0x5)) 100 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 101 FTIM1_NOR_TRAD_NOR(0x1a) | \ 102 FTIM1_NOR_TSEQRAD_NOR(0x13)) 103 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 104 FTIM2_NOR_TCH(0x8) | \ 105 FTIM2_NOR_TWPH(0xe) | \ 106 FTIM2_NOR_TWP(0x1c)) 107 #define CONFIG_SYS_NOR_FTIM3 0x04000000 108 #define CONFIG_SYS_IFC_CCR 0x01000000 109 110 #ifndef SYS_NO_FLASH 111 #define CONFIG_SYS_FLASH_QUIET_TEST 112 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 113 114 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 119 #define CONFIG_SYS_FLASH_EMPTY_INFO 120 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 121 CONFIG_SYS_FLASH_BASE + 0x40000000} 122 #endif 123 #endif 124 125 #define CONFIG_NAND_FSL_IFC 126 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 127 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 128 129 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 130 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 131 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 132 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 133 | CSPR_V) 134 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 135 136 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 137 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 138 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 139 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 140 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 141 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 142 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 143 144 #define CONFIG_SYS_NAND_ONFI_DETECTION 145 146 /* ONFI NAND Flash mode0 Timing Params */ 147 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 148 FTIM0_NAND_TWP(0x18) | \ 149 FTIM0_NAND_TWCHT(0x07) | \ 150 FTIM0_NAND_TWH(0x0a)) 151 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 152 FTIM1_NAND_TWBE(0x39) | \ 153 FTIM1_NAND_TRR(0x0e) | \ 154 FTIM1_NAND_TRP(0x18)) 155 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 156 FTIM2_NAND_TREH(0x0a) | \ 157 FTIM2_NAND_TWHRE(0x1e)) 158 #define CONFIG_SYS_NAND_FTIM3 0x0 159 160 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 162 #define CONFIG_MTD_NAND_VERIFY_WRITE 163 #define CONFIG_CMD_NAND 164 165 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 166 167 #define CONFIG_FSL_QIXIS 168 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 169 #define QIXIS_LBMAP_SWITCH 6 170 #define QIXIS_QMAP_MASK 0xe0 171 #define QIXIS_QMAP_SHIFT 5 172 #define QIXIS_LBMAP_MASK 0x0f 173 #define QIXIS_LBMAP_SHIFT 0 174 #define QIXIS_LBMAP_DFLTBANK 0x0e 175 #define QIXIS_LBMAP_ALTBANK 0x2e 176 #define QIXIS_LBMAP_SD 0x00 177 #define QIXIS_LBMAP_EMMC 0x00 178 #define QIXIS_LBMAP_IFC 0x00 179 #define QIXIS_LBMAP_SD_QSPI 0x0e 180 #define QIXIS_LBMAP_QSPI 0x0e 181 #define QIXIS_RCW_SRC_IFC 0x25 182 #define QIXIS_RCW_SRC_SD 0x40 183 #define QIXIS_RCW_SRC_EMMC 0x41 184 #define QIXIS_RCW_SRC_QSPI 0x62 185 #define QIXIS_RST_CTL_RESET 0x41 186 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 187 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 188 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 189 #define QIXIS_RST_FORCE_MEM 0x01 190 #define QIXIS_STAT_PRES1 0xb 191 #define QIXIS_SDID_MASK 0x07 192 #define QIXIS_ESDHC_NO_ADAPTER 0x7 193 194 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 195 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 196 | CSPR_PORT_SIZE_8 \ 197 | CSPR_MSEL_GPCM \ 198 | CSPR_V) 199 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 200 | CSPR_PORT_SIZE_8 \ 201 | CSPR_MSEL_GPCM \ 202 | CSPR_V) 203 204 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 205 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 206 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 207 #else 208 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 209 #endif 210 /* QIXIS Timing parameters*/ 211 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 212 FTIM0_GPCM_TEADC(0x0e) | \ 213 FTIM0_GPCM_TEAHC(0x0e)) 214 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 215 FTIM1_GPCM_TRAD(0x3f)) 216 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 217 FTIM2_GPCM_TCH(0xf) | \ 218 FTIM2_GPCM_TWP(0x3E)) 219 #define SYS_FPGA_CS_FTIM3 0x0 220 221 #ifdef CONFIG_TFABOOT 222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 224 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 225 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 226 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 227 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 228 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 229 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 230 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 231 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 232 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 233 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 234 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 235 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 236 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 237 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 238 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 239 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 240 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 241 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 242 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 243 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 244 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 245 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 246 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 247 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 248 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 249 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 250 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 251 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 252 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 253 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 254 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 255 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 256 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 257 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 258 #else 259 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 260 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 261 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 262 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 263 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 264 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 265 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 266 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 267 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 268 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 269 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 270 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 271 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 272 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 273 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 274 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 275 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 276 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 277 #else 278 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 279 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 280 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 281 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 282 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 283 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 284 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 285 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 286 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 287 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 289 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 290 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 291 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 297 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 298 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 299 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 300 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 301 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 302 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 303 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 304 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 305 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 306 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 307 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 308 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 309 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 310 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 311 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 312 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 313 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 314 #endif 315 #endif 316 317 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 318 319 /* 320 * I2C bus multiplexer 321 */ 322 #define I2C_MUX_PCA_ADDR_PRI 0x77 323 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 324 #define I2C_RETIMER_ADDR 0x18 325 #define I2C_RETIMER_ADDR2 0x19 326 #define I2C_MUX_CH_DEFAULT 0x8 327 #define I2C_MUX_CH5 0xD 328 329 #define I2C_MUX_CH_VOL_MONITOR 0xA 330 331 /* Voltage monitor on channel 2*/ 332 #define I2C_VOL_MONITOR_ADDR 0x63 333 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 334 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 335 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 336 #define I2C_SVDD_MONITOR_ADDR 0x4F 337 338 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 339 #define CONFIG_VID 340 341 /* The lowest and highest voltage allowed for LS1088AQDS */ 342 #define VDD_MV_MIN 819 343 #define VDD_MV_MAX 1212 344 345 #define CONFIG_VOL_MONITOR_LTC3882_SET 346 #define CONFIG_VOL_MONITOR_LTC3882_READ 347 348 /* PM Bus commands code for LTC3882*/ 349 #define PMBUS_CMD_PAGE 0x0 350 #define PMBUS_CMD_READ_VOUT 0x8B 351 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 352 #define PMBUS_CMD_VOUT_COMMAND 0x21 353 354 #define PWM_CHANNEL0 0x0 355 356 /* 357 * RTC configuration 358 */ 359 #define RTC 360 #define CONFIG_RTC_PCF8563 1 361 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 362 #define CONFIG_CMD_DATE 363 364 /* EEPROM */ 365 #define CONFIG_ID_EEPROM 366 #define CONFIG_SYS_I2C_EEPROM_NXID 367 #define CONFIG_SYS_EEPROM_BUS_NUM 0 368 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 369 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 370 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 371 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 372 373 /* QSPI device */ 374 #if defined(CONFIG_TFABOOT) || \ 375 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 376 #define FSL_QSPI_FLASH_SIZE (1 << 26) 377 #define FSL_QSPI_FLASH_NUM 2 378 379 #endif 380 381 #ifdef CONFIG_FSL_DSPI 382 #define CONFIG_SPI_FLASH_STMICRO 383 #define CONFIG_SPI_FLASH_SST 384 #define CONFIG_SPI_FLASH_EON 385 #if !defined(CONFIG_TFABOOT) && \ 386 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 387 #endif 388 #endif 389 390 #define CONFIG_CMD_MEMINFO 391 #define CONFIG_SYS_MEMTEST_START 0x80000000 392 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 393 394 #ifdef CONFIG_SPL_BUILD 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 396 #else 397 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 398 #endif 399 400 #define CONFIG_FSL_MEMAC 401 402 /* MMC */ 403 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 404 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 405 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 406 407 /* Initial environment variables */ 408 #ifdef CONFIG_SECURE_BOOT 409 #undef CONFIG_EXTRA_ENV_SETTINGS 410 #define CONFIG_EXTRA_ENV_SETTINGS \ 411 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 412 "loadaddr=0x90100000\0" \ 413 "kernel_addr=0x100000\0" \ 414 "ramdisk_addr=0x800000\0" \ 415 "ramdisk_size=0x2000000\0" \ 416 "fdt_high=0xa0000000\0" \ 417 "initrd_high=0xffffffffffffffff\0" \ 418 "kernel_start=0x1000000\0" \ 419 "kernel_load=0xa0000000\0" \ 420 "kernel_size=0x2800000\0" \ 421 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 422 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ 423 "sf read 0xa0e00000 0xe00000 0x100000;" \ 424 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ 425 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 426 "mcmemsize=0x70000000 \0" 427 #else /* if !(CONFIG_SECURE_BOOT) */ 428 #ifdef CONFIG_TFABOOT 429 #define QSPI_MC_INIT_CMD \ 430 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 431 "sf read 0x80100000 0xE00000 0x100000;" \ 432 "fsl_mc start mc 0x80000000 0x80100000\0" 433 #define SD_MC_INIT_CMD \ 434 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 435 "mmc read 0x80100000 0x7000 0x800;" \ 436 "fsl_mc start mc 0x80000000 0x80100000\0" 437 #define IFC_MC_INIT_CMD \ 438 "fsl_mc start mc 0x580A00000 0x580E00000\0" 439 440 #undef CONFIG_EXTRA_ENV_SETTINGS 441 #define CONFIG_EXTRA_ENV_SETTINGS \ 442 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 443 "loadaddr=0x90100000\0" \ 444 "kernel_addr=0x100000\0" \ 445 "kernel_addr_sd=0x800\0" \ 446 "ramdisk_addr=0x800000\0" \ 447 "ramdisk_size=0x2000000\0" \ 448 "fdt_high=0xa0000000\0" \ 449 "initrd_high=0xffffffffffffffff\0" \ 450 "kernel_start=0x1000000\0" \ 451 "kernel_start_sd=0x8000\0" \ 452 "kernel_load=0xa0000000\0" \ 453 "kernel_size=0x2800000\0" \ 454 "kernel_size_sd=0x14000\0" \ 455 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 456 "sf read 0x80100000 0xE00000 0x100000;" \ 457 "fsl_mc start mc 0x80000000 0x80100000\0" \ 458 "mcmemsize=0x70000000 \0" 459 #define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \ 460 "sf read 0x80001000 0xd00000 0x100000;"\ 461 " fsl_mc lazyapply dpl 0x80001000 &&" \ 462 " sf read $kernel_load $kernel_start" \ 463 " $kernel_size && bootm $kernel_load" 464 #define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ 465 " fsl_mc lazyapply dpl 0x80001000 &&" \ 466 " mmc read $kernel_load $kernel_start_sd" \ 467 " $kernel_size_sd && bootm $kernel_load" 468 #define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ 469 " cp.b $kernel_start $kernel_load" \ 470 " $kernel_size && bootm $kernel_load" 471 #else 472 #if defined(CONFIG_QSPI_BOOT) 473 #undef CONFIG_EXTRA_ENV_SETTINGS 474 #define CONFIG_EXTRA_ENV_SETTINGS \ 475 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 476 "loadaddr=0x90100000\0" \ 477 "kernel_addr=0x100000\0" \ 478 "ramdisk_addr=0x800000\0" \ 479 "ramdisk_size=0x2000000\0" \ 480 "fdt_high=0xa0000000\0" \ 481 "initrd_high=0xffffffffffffffff\0" \ 482 "kernel_start=0x1000000\0" \ 483 "kernel_load=0xa0000000\0" \ 484 "kernel_size=0x2800000\0" \ 485 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 486 "sf read 0x80100000 0xE00000 0x100000;" \ 487 "fsl_mc start mc 0x80000000 0x80100000\0" \ 488 "mcmemsize=0x70000000 \0" 489 #elif defined(CONFIG_SD_BOOT) 490 #undef CONFIG_EXTRA_ENV_SETTINGS 491 #define CONFIG_EXTRA_ENV_SETTINGS \ 492 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 493 "loadaddr=0x90100000\0" \ 494 "kernel_addr=0x800\0" \ 495 "ramdisk_addr=0x800000\0" \ 496 "ramdisk_size=0x2000000\0" \ 497 "fdt_high=0xa0000000\0" \ 498 "initrd_high=0xffffffffffffffff\0" \ 499 "kernel_start=0x8000\0" \ 500 "kernel_load=0xa0000000\0" \ 501 "kernel_size=0x14000\0" \ 502 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 503 "mmc read 0x80100000 0x7000 0x800;" \ 504 "fsl_mc start mc 0x80000000 0x80100000\0" \ 505 "mcmemsize=0x70000000 \0" 506 #else /* NOR BOOT */ 507 #undef CONFIG_EXTRA_ENV_SETTINGS 508 #define CONFIG_EXTRA_ENV_SETTINGS \ 509 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 510 "loadaddr=0x90100000\0" \ 511 "kernel_addr=0x100000\0" \ 512 "ramdisk_addr=0x800000\0" \ 513 "ramdisk_size=0x2000000\0" \ 514 "fdt_high=0xa0000000\0" \ 515 "initrd_high=0xffffffffffffffff\0" \ 516 "kernel_start=0x1000000\0" \ 517 "kernel_load=0xa0000000\0" \ 518 "kernel_size=0x2800000\0" \ 519 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 520 "mcmemsize=0x70000000 \0" 521 #endif 522 #endif /* CONFIG_TFABOOT */ 523 #endif /* CONFIG_SECURE_BOOT */ 524 525 #ifdef CONFIG_FSL_MC_ENET 526 #define CONFIG_FSL_MEMAC 527 #define CONFIG_PHYLIB 528 #define CONFIG_PHYLIB_10G 529 #define CONFIG_PHY_VITESSE 530 #define CONFIG_PHY_REALTEK 531 #define CONFIG_PHY_TERANETICS 532 #define RGMII_PHY1_ADDR 0x1 533 #define RGMII_PHY2_ADDR 0x2 534 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 535 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 536 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 537 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 538 539 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 540 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 541 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 542 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 543 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 544 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 545 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 546 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 547 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 548 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 549 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 550 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 551 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 552 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 553 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 554 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 555 556 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 557 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 558 559 #endif 560 561 #define BOOT_TARGET_DEVICES(func) \ 562 func(USB, usb, 0) \ 563 func(MMC, mmc, 0) \ 564 func(SCSI, scsi, 0) \ 565 func(DHCP, dhcp, na) 566 #include <config_distro_bootcmd.h> 567 568 #include <asm/fsl_secure_boot.h> 569 570 #endif /* __LS1088A_QDS_H */ 571