1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 */ 5 6 #ifndef __LS1088A_QDS_H 7 #define __LS1088A_QDS_H 8 9 #include "ls1088a_common.h" 10 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 18 #if defined(CONFIG_QSPI_BOOT) 19 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 20 #define CONFIG_ENV_SECT_SIZE 0x40000 21 #elif defined(CONFIG_SD_BOOT) 22 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 23 #define CONFIG_SYS_MMC_ENV_DEV 0 24 #define CONFIG_ENV_SIZE 0x2000 25 #else 26 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 27 #define CONFIG_ENV_SECT_SIZE 0x20000 28 #define CONFIG_ENV_SIZE 0x20000 29 #endif 30 31 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 32 #define CONFIG_QIXIS_I2C_ACCESS 33 #define SYS_NO_FLASH 34 35 #undef CONFIG_CMD_IMLS 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_DDR_CLK_FREQ 100000000 38 #else 39 #define CONFIG_QIXIS_I2C_ACCESS 40 #define CONFIG_SYS_I2C_EARLY_INIT 41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 43 #endif 44 45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 46 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 47 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 49 50 #define CONFIG_DDR_SPD 51 #define CONFIG_DDR_ECC 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 53 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 54 #define SPD_EEPROM_ADDRESS 0x51 55 #define CONFIG_SYS_SPD_BUS_NUM 0 56 57 58 /* 59 * IFC Definitions 60 */ 61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 65 66 #define CONFIG_SYS_NOR0_CSPR \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 73 CSPR_PORT_SIZE_16 | \ 74 CSPR_MSEL_NOR | \ 75 CSPR_V) 76 #define CONFIG_SYS_NOR1_CSPR \ 77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 78 CSPR_PORT_SIZE_16 | \ 79 CSPR_MSEL_NOR | \ 80 CSPR_V) 81 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 83 CSPR_PORT_SIZE_16 | \ 84 CSPR_MSEL_NOR | \ 85 CSPR_V) 86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 88 FTIM0_NOR_TEADC(0x5) | \ 89 FTIM0_NOR_TAVDS(0x6) | \ 90 FTIM0_NOR_TEAHC(0x5)) 91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) | \ 93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 95 FTIM2_NOR_TCH(0x8) | \ 96 FTIM2_NOR_TWPH(0xe) | \ 97 FTIM2_NOR_TWP(0x1c)) 98 #define CONFIG_SYS_NOR_FTIM3 0x04000000 99 #define CONFIG_SYS_IFC_CCR 0x01000000 100 101 #ifndef SYS_NO_FLASH 102 #define CONFIG_SYS_FLASH_QUIET_TEST 103 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 104 105 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 106 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 107 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 108 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 109 110 #define CONFIG_SYS_FLASH_EMPTY_INFO 111 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 112 CONFIG_SYS_FLASH_BASE + 0x40000000} 113 #endif 114 #endif 115 116 #define CONFIG_NAND_FSL_IFC 117 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 118 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 119 120 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 121 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 122 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 123 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 124 | CSPR_V) 125 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 126 127 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 128 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 129 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 130 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 131 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 132 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 133 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 134 135 #define CONFIG_SYS_NAND_ONFI_DETECTION 136 137 /* ONFI NAND Flash mode0 Timing Params */ 138 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 139 FTIM0_NAND_TWP(0x18) | \ 140 FTIM0_NAND_TWCHT(0x07) | \ 141 FTIM0_NAND_TWH(0x0a)) 142 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 143 FTIM1_NAND_TWBE(0x39) | \ 144 FTIM1_NAND_TRR(0x0e) | \ 145 FTIM1_NAND_TRP(0x18)) 146 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 147 FTIM2_NAND_TREH(0x0a) | \ 148 FTIM2_NAND_TWHRE(0x1e)) 149 #define CONFIG_SYS_NAND_FTIM3 0x0 150 151 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_MTD_NAND_VERIFY_WRITE 154 #define CONFIG_CMD_NAND 155 156 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 157 158 #define CONFIG_FSL_QIXIS 159 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 160 #define QIXIS_LBMAP_SWITCH 6 161 #define QIXIS_QMAP_MASK 0xe0 162 #define QIXIS_QMAP_SHIFT 5 163 #define QIXIS_LBMAP_MASK 0x0f 164 #define QIXIS_LBMAP_SHIFT 0 165 #define QIXIS_LBMAP_DFLTBANK 0x0e 166 #define QIXIS_LBMAP_ALTBANK 0x2e 167 #define QIXIS_LBMAP_SD 0x00 168 #define QIXIS_LBMAP_EMMC 0x00 169 #define QIXIS_LBMAP_IFC 0x00 170 #define QIXIS_LBMAP_SD_QSPI 0x0e 171 #define QIXIS_LBMAP_QSPI 0x0e 172 #define QIXIS_RCW_SRC_IFC 0x25 173 #define QIXIS_RCW_SRC_SD 0x40 174 #define QIXIS_RCW_SRC_EMMC 0x41 175 #define QIXIS_RCW_SRC_QSPI 0x62 176 #define QIXIS_RST_CTL_RESET 0x41 177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 178 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 180 #define QIXIS_RST_FORCE_MEM 0x01 181 #define QIXIS_STAT_PRES1 0xb 182 #define QIXIS_SDID_MASK 0x07 183 #define QIXIS_ESDHC_NO_ADAPTER 0x7 184 185 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 186 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 187 | CSPR_PORT_SIZE_8 \ 188 | CSPR_MSEL_GPCM \ 189 | CSPR_V) 190 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 191 | CSPR_PORT_SIZE_8 \ 192 | CSPR_MSEL_GPCM \ 193 | CSPR_V) 194 195 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 196 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 197 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 198 #else 199 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 200 #endif 201 /* QIXIS Timing parameters*/ 202 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 203 FTIM0_GPCM_TEADC(0x0e) | \ 204 FTIM0_GPCM_TEAHC(0x0e)) 205 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 206 FTIM1_GPCM_TRAD(0x3f)) 207 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 208 FTIM2_GPCM_TCH(0xf) | \ 209 FTIM2_GPCM_TWP(0x3E)) 210 #define SYS_FPGA_CS_FTIM3 0x0 211 212 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 213 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 214 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 215 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 216 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 217 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 218 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 219 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 220 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 221 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 222 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 223 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 224 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 225 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 226 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 227 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 228 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 229 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 230 #else 231 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 232 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 233 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 234 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 235 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 236 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 237 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 238 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 239 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 240 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 241 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 242 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 243 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 244 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 245 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 246 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 247 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 248 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 249 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 250 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 251 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 252 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 253 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 254 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 255 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 256 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 257 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 258 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 259 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 260 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 261 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 262 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 263 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 264 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 265 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 266 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 267 #endif 268 269 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 270 271 /* 272 * I2C bus multiplexer 273 */ 274 #define I2C_MUX_PCA_ADDR_PRI 0x77 275 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 276 #define I2C_RETIMER_ADDR 0x18 277 #define I2C_RETIMER_ADDR2 0x19 278 #define I2C_MUX_CH_DEFAULT 0x8 279 #define I2C_MUX_CH5 0xD 280 281 #define I2C_MUX_CH_VOL_MONITOR 0xA 282 283 /* Voltage monitor on channel 2*/ 284 #define I2C_VOL_MONITOR_ADDR 0x63 285 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 286 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 287 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 288 #define I2C_SVDD_MONITOR_ADDR 0x4F 289 290 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 291 #define CONFIG_VID 292 293 /* The lowest and highest voltage allowed for LS1088AQDS */ 294 #define VDD_MV_MIN 819 295 #define VDD_MV_MAX 1212 296 297 #define CONFIG_VOL_MONITOR_LTC3882_SET 298 #define CONFIG_VOL_MONITOR_LTC3882_READ 299 300 /* PM Bus commands code for LTC3882*/ 301 #define PMBUS_CMD_PAGE 0x0 302 #define PMBUS_CMD_READ_VOUT 0x8B 303 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 304 #define PMBUS_CMD_VOUT_COMMAND 0x21 305 306 #define PWM_CHANNEL0 0x0 307 308 /* 309 * RTC configuration 310 */ 311 #define RTC 312 #define CONFIG_RTC_PCF8563 1 313 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 314 #define CONFIG_CMD_DATE 315 316 /* EEPROM */ 317 #define CONFIG_ID_EEPROM 318 #define CONFIG_SYS_I2C_EEPROM_NXID 319 #define CONFIG_SYS_EEPROM_BUS_NUM 0 320 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 321 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 322 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 324 325 /* QSPI device */ 326 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 327 #define CONFIG_FSL_QSPI 328 #define FSL_QSPI_FLASH_SIZE (1 << 26) 329 #define FSL_QSPI_FLASH_NUM 2 330 331 #endif 332 333 #ifdef CONFIG_FSL_DSPI 334 #define CONFIG_SPI_FLASH_STMICRO 335 #define CONFIG_SPI_FLASH_SST 336 #define CONFIG_SPI_FLASH_EON 337 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 338 #define CONFIG_SF_DEFAULT_BUS 1 339 #define CONFIG_SF_DEFAULT_CS 0 340 #endif 341 #endif 342 343 #define CONFIG_CMD_MEMINFO 344 #define CONFIG_SYS_MEMTEST_START 0x80000000 345 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 346 347 #ifdef CONFIG_SPL_BUILD 348 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 349 #else 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 351 #endif 352 353 #define CONFIG_FSL_MEMAC 354 355 /* MMC */ 356 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 357 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 358 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 359 360 /* Initial environment variables */ 361 #ifdef CONFIG_SECURE_BOOT 362 #undef CONFIG_EXTRA_ENV_SETTINGS 363 #define CONFIG_EXTRA_ENV_SETTINGS \ 364 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 365 "loadaddr=0x90100000\0" \ 366 "kernel_addr=0x100000\0" \ 367 "ramdisk_addr=0x800000\0" \ 368 "ramdisk_size=0x2000000\0" \ 369 "fdt_high=0xa0000000\0" \ 370 "initrd_high=0xffffffffffffffff\0" \ 371 "kernel_start=0x1000000\0" \ 372 "kernel_load=0xa0000000\0" \ 373 "kernel_size=0x2800000\0" \ 374 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 375 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ 376 "sf read 0xa0e00000 0xe00000 0x100000;" \ 377 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ 378 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 379 "mcmemsize=0x70000000 \0" 380 #else /* if !(CONFIG_SECURE_BOOT) */ 381 #if defined(CONFIG_QSPI_BOOT) 382 #undef CONFIG_EXTRA_ENV_SETTINGS 383 #define CONFIG_EXTRA_ENV_SETTINGS \ 384 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 385 "loadaddr=0x90100000\0" \ 386 "kernel_addr=0x100000\0" \ 387 "ramdisk_addr=0x800000\0" \ 388 "ramdisk_size=0x2000000\0" \ 389 "fdt_high=0xa0000000\0" \ 390 "initrd_high=0xffffffffffffffff\0" \ 391 "kernel_start=0x1000000\0" \ 392 "kernel_load=0xa0000000\0" \ 393 "kernel_size=0x2800000\0" \ 394 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 395 "sf read 0x80100000 0xE00000 0x100000;" \ 396 "fsl_mc start mc 0x80000000 0x80100000\0" \ 397 "mcmemsize=0x70000000 \0" 398 #elif defined(CONFIG_SD_BOOT) 399 #undef CONFIG_EXTRA_ENV_SETTINGS 400 #define CONFIG_EXTRA_ENV_SETTINGS \ 401 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 402 "loadaddr=0x90100000\0" \ 403 "kernel_addr=0x800\0" \ 404 "ramdisk_addr=0x800000\0" \ 405 "ramdisk_size=0x2000000\0" \ 406 "fdt_high=0xa0000000\0" \ 407 "initrd_high=0xffffffffffffffff\0" \ 408 "kernel_start=0x8000\0" \ 409 "kernel_load=0xa0000000\0" \ 410 "kernel_size=0x14000\0" \ 411 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 412 "mmc read 0x80100000 0x7000 0x800;" \ 413 "fsl_mc start mc 0x80000000 0x80100000\0" \ 414 "mcmemsize=0x70000000 \0" 415 #else /* NOR BOOT */ 416 #undef CONFIG_EXTRA_ENV_SETTINGS 417 #define CONFIG_EXTRA_ENV_SETTINGS \ 418 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 419 "loadaddr=0x90100000\0" \ 420 "kernel_addr=0x100000\0" \ 421 "ramdisk_addr=0x800000\0" \ 422 "ramdisk_size=0x2000000\0" \ 423 "fdt_high=0xa0000000\0" \ 424 "initrd_high=0xffffffffffffffff\0" \ 425 "kernel_start=0x1000000\0" \ 426 "kernel_load=0xa0000000\0" \ 427 "kernel_size=0x2800000\0" \ 428 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 429 "mcmemsize=0x70000000 \0" 430 #endif 431 #endif /* CONFIG_SECURE_BOOT */ 432 433 #ifdef CONFIG_FSL_MC_ENET 434 #define CONFIG_FSL_MEMAC 435 #define CONFIG_PHYLIB 436 #define CONFIG_PHYLIB_10G 437 #define CONFIG_PHY_VITESSE 438 #define CONFIG_PHY_REALTEK 439 #define CONFIG_PHY_TERANETICS 440 #define RGMII_PHY1_ADDR 0x1 441 #define RGMII_PHY2_ADDR 0x2 442 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 443 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 444 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 445 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 446 447 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 448 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 449 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 450 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 451 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 452 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 453 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 454 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 455 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 456 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 457 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 458 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 459 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 460 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 461 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 462 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 463 464 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 465 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 466 467 #endif 468 469 #define BOOT_TARGET_DEVICES(func) \ 470 func(USB, usb, 0) \ 471 func(MMC, mmc, 0) \ 472 func(SCSI, scsi, 0) \ 473 func(DHCP, dhcp, na) 474 #include <config_distro_bootcmd.h> 475 476 #include <asm/fsl_secure_boot.h> 477 478 #endif /* __LS1088A_QDS_H */ 479