1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_QDS_H 8 #define __LS1088A_QDS_H 9 10 #include "ls1088a_common.h" 11 12 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 16 #ifndef __ASSEMBLY__ 17 unsigned long get_board_sys_clk(void); 18 unsigned long get_board_ddr_clk(void); 19 #endif 20 21 22 #if defined(CONFIG_QSPI_BOOT) 23 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 24 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 25 #define CONFIG_ENV_SECT_SIZE 0x40000 26 #elif defined(CONFIG_SD_BOOT) 27 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 28 #define CONFIG_SYS_MMC_ENV_DEV 0 29 #define CONFIG_ENV_SIZE 0x2000 30 #else 31 #define CONFIG_ENV_IS_IN_FLASH 32 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 33 #define CONFIG_ENV_SECT_SIZE 0x20000 34 #define CONFIG_ENV_SIZE 0x20000 35 #endif 36 37 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 38 #define CONFIG_QIXIS_I2C_ACCESS 39 #define SYS_NO_FLASH 40 41 #undef CONFIG_CMD_IMLS 42 #define CONFIG_SYS_CLK_FREQ 100000000 43 #define CONFIG_DDR_CLK_FREQ 100000000 44 #else 45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 47 #endif 48 49 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 50 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 51 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 54 #define CONFIG_DDR_SPD 55 #define CONFIG_DDR_ECC 56 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 58 #define SPD_EEPROM_ADDRESS 0x51 59 #define CONFIG_SYS_SPD_BUS_NUM 0 60 61 62 /* 63 * IFC Definitions 64 */ 65 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 66 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 67 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 68 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 69 70 #define CONFIG_SYS_NOR0_CSPR \ 71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 72 CSPR_PORT_SIZE_16 | \ 73 CSPR_MSEL_NOR | \ 74 CSPR_V) 75 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 77 CSPR_PORT_SIZE_16 | \ 78 CSPR_MSEL_NOR | \ 79 CSPR_V) 80 #define CONFIG_SYS_NOR1_CSPR \ 81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 86 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 87 CSPR_PORT_SIZE_16 | \ 88 CSPR_MSEL_NOR | \ 89 CSPR_V) 90 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 91 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 92 FTIM0_NOR_TEADC(0x5) | \ 93 FTIM0_NOR_TEAHC(0x5)) 94 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 95 FTIM1_NOR_TRAD_NOR(0x1a) |\ 96 FTIM1_NOR_TSEQRAD_NOR(0x13)) 97 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 98 FTIM2_NOR_TCH(0x4) | \ 99 FTIM2_NOR_TWPH(0x0E) | \ 100 FTIM2_NOR_TWP(0x1c)) 101 #define CONFIG_SYS_NOR_FTIM3 0x04000000 102 #define CONFIG_SYS_IFC_CCR 0x01000000 103 104 #ifndef SYS_NO_FLASH 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 108 #define CONFIG_SYS_FLASH_QUIET_TEST 109 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 110 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 115 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 118 CONFIG_SYS_FLASH_BASE + 0x40000000} 119 #endif 120 #endif 121 122 #define CONFIG_NAND_FSL_IFC 123 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 124 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 125 126 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 127 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 128 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 129 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 130 | CSPR_V) 131 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 132 133 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 134 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 135 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 136 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 137 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 138 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 139 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 140 141 #define CONFIG_SYS_NAND_ONFI_DETECTION 142 143 /* ONFI NAND Flash mode0 Timing Params */ 144 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 145 FTIM0_NAND_TWP(0x18) | \ 146 FTIM0_NAND_TWCHT(0x07) | \ 147 FTIM0_NAND_TWH(0x0a)) 148 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 149 FTIM1_NAND_TWBE(0x39) | \ 150 FTIM1_NAND_TRR(0x0e) | \ 151 FTIM1_NAND_TRP(0x18)) 152 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 153 FTIM2_NAND_TREH(0x0a) | \ 154 FTIM2_NAND_TWHRE(0x1e)) 155 #define CONFIG_SYS_NAND_FTIM3 0x0 156 157 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 159 #define CONFIG_MTD_NAND_VERIFY_WRITE 160 #define CONFIG_CMD_NAND 161 162 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 163 164 #define CONFIG_FSL_QIXIS 165 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 166 #define QIXIS_LBMAP_SWITCH 6 167 #define QIXIS_QMAP_MASK 0xe0 168 #define QIXIS_QMAP_SHIFT 5 169 #define QIXIS_LBMAP_MASK 0x0f 170 #define QIXIS_LBMAP_SHIFT 0 171 #define QIXIS_LBMAP_DFLTBANK 0x0e 172 #define QIXIS_LBMAP_ALTBANK 0x2e 173 #define QIXIS_LBMAP_SD 0x00 174 #define QIXIS_LBMAP_SD_QSPI 0x0e 175 #define QIXIS_LBMAP_QSPI 0x0e 176 #define QIXIS_RCW_SRC_SD 0x40 177 #define QIXIS_RCW_SRC_QSPI 0x62 178 #define QIXIS_RST_CTL_RESET 0x41 179 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 180 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 181 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 182 #define QIXIS_RST_FORCE_MEM 0x01 183 #define QIXIS_STAT_PRES1 0xb 184 #define QIXIS_SDID_MASK 0x07 185 #define QIXIS_ESDHC_NO_ADAPTER 0x7 186 187 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 188 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 189 | CSPR_PORT_SIZE_8 \ 190 | CSPR_MSEL_GPCM \ 191 | CSPR_V) 192 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 193 | CSPR_PORT_SIZE_8 \ 194 | CSPR_MSEL_GPCM \ 195 | CSPR_V) 196 197 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 198 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 199 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 200 #else 201 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 202 #endif 203 /* QIXIS Timing parameters*/ 204 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 205 FTIM0_GPCM_TEADC(0x0e) | \ 206 FTIM0_GPCM_TEAHC(0x0e)) 207 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 208 FTIM1_GPCM_TRAD(0x3f)) 209 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 210 FTIM2_GPCM_TCH(0xf) | \ 211 FTIM2_GPCM_TWP(0x3E)) 212 #define SYS_FPGA_CS_FTIM3 0x0 213 214 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 223 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 224 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 225 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 226 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 227 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 228 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 229 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 230 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 231 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 232 #else 233 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 234 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 235 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 236 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 237 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 238 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 239 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 240 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 241 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 242 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 243 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 244 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 245 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 246 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 247 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 248 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 249 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 250 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 251 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 252 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 253 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 254 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 255 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 256 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 257 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 258 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 259 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 260 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 261 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 262 #define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL 263 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 264 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 265 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 266 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 267 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 268 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 269 #endif 270 271 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 272 273 /* 274 * I2C bus multiplexer 275 */ 276 #define I2C_MUX_PCA_ADDR_PRI 0x77 277 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 278 #define I2C_RETIMER_ADDR 0x18 279 #define I2C_RETIMER_ADDR2 0x19 280 #define I2C_MUX_CH_DEFAULT 0x8 281 #define I2C_MUX_CH5 0xD 282 283 /* 284 * RTC configuration 285 */ 286 #define RTC 287 #define CONFIG_RTC_PCF8563 1 288 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 289 #define CONFIG_CMD_DATE 290 291 /* EEPROM */ 292 #define CONFIG_ID_EEPROM 293 #define CONFIG_SYS_I2C_EEPROM_NXID 294 #define CONFIG_SYS_EEPROM_BUS_NUM 0 295 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 296 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 298 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 299 300 /* QSPI device */ 301 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 302 #define CONFIG_FSL_QSPI 303 #define FSL_QSPI_FLASH_SIZE (1 << 26) 304 #define FSL_QSPI_FLASH_NUM 2 305 306 #endif 307 308 #ifdef CONFIG_FSL_DSPI 309 #define CONFIG_SPI_FLASH_STMICRO 310 #define CONFIG_SPI_FLASH_SST 311 #define CONFIG_SPI_FLASH_EON 312 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 313 #define CONFIG_SF_DEFAULT_BUS 1 314 #define CONFIG_SF_DEFAULT_CS 0 315 #endif 316 #endif 317 318 #define CONFIG_CMD_MEMINFO 319 #define CONFIG_CMD_MEMTEST 320 #define CONFIG_SYS_MEMTEST_START 0x80000000 321 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 322 323 #ifdef CONFIG_SPL_BUILD 324 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 325 #else 326 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 327 #endif 328 329 #define CONFIG_FSL_MEMAC 330 331 /* MMC */ 332 #define CONFIG_FSL_ESDHC 333 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 334 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 335 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 336 337 /* Initial environment variables */ 338 #if defined(CONFIG_QSPI_BOOT) 339 #undef CONFIG_EXTRA_ENV_SETTINGS 340 #define CONFIG_EXTRA_ENV_SETTINGS \ 341 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 342 "loadaddr=0x90100000\0" \ 343 "kernel_addr=0x100000\0" \ 344 "ramdisk_addr=0x800000\0" \ 345 "ramdisk_size=0x2000000\0" \ 346 "fdt_high=0xa0000000\0" \ 347 "initrd_high=0xffffffffffffffff\0" \ 348 "kernel_start=0x1000000\0" \ 349 "kernel_load=0xa0000000\0" \ 350 "kernel_size=0x2800000\0" \ 351 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 352 "sf read 0x80100000 0xE00000 0x100000;" \ 353 "fsl_mc start mc 0x80000000 0x80100000\0" \ 354 "mcmemsize=0x70000000 \0" 355 #elif defined(CONFIG_SD_BOOT) 356 #undef CONFIG_EXTRA_ENV_SETTINGS 357 #define CONFIG_EXTRA_ENV_SETTINGS \ 358 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 359 "loadaddr=0x90100000\0" \ 360 "kernel_addr=0x800\0" \ 361 "ramdisk_addr=0x800000\0" \ 362 "ramdisk_size=0x2000000\0" \ 363 "fdt_high=0xa0000000\0" \ 364 "initrd_high=0xffffffffffffffff\0" \ 365 "kernel_start=0x8000\0" \ 366 "kernel_load=0xa0000000\0" \ 367 "kernel_size=0x14000\0" \ 368 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 369 "mmc read 0x80100000 0x7000 0x800;" \ 370 "fsl_mc start mc 0x80000000 0x80100000\0" \ 371 "mcmemsize=0x70000000 \0" 372 #else /* NOR BOOT */ 373 #undef CONFIG_EXTRA_ENV_SETTINGS 374 #define CONFIG_EXTRA_ENV_SETTINGS \ 375 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 376 "loadaddr=0x90100000\0" \ 377 "kernel_addr=0x100000\0" \ 378 "ramdisk_addr=0x800000\0" \ 379 "ramdisk_size=0x2000000\0" \ 380 "fdt_high=0xa0000000\0" \ 381 "initrd_high=0xffffffffffffffff\0" \ 382 "kernel_start=0x1000000\0" \ 383 "kernel_load=0xa0000000\0" \ 384 "kernel_size=0x2800000\0" \ 385 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 386 "mcmemsize=0x70000000 \0" 387 #endif 388 389 #ifdef CONFIG_FSL_MC_ENET 390 #define CONFIG_FSL_MEMAC 391 #define CONFIG_PHYLIB 392 #define CONFIG_PHYLIB_10G 393 #define CONFIG_PHY_VITESSE 394 #define CONFIG_PHY_REALTEK 395 #define CONFIG_PHY_TERANETICS 396 #define RGMII_PHY1_ADDR 0x1 397 #define RGMII_PHY2_ADDR 0x2 398 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 399 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 400 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 401 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 402 403 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 404 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 405 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 406 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 407 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 408 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 409 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 410 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 411 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 412 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 413 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 414 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 415 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 416 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 417 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 418 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 419 420 #define CONFIG_MII /* MII PHY management */ 421 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 422 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 423 424 #endif 425 426 #undef CONFIG_CMDLINE_EDITING 427 #include <config_distro_defaults.h> 428 #define BOOT_TARGET_DEVICES(func) \ 429 func(USB, usb, 0) \ 430 func(MMC, mmc, 0) \ 431 func(SCSI, scsi, 0) \ 432 func(DHCP, dhcp, na) 433 #include <config_distro_bootcmd.h> 434 435 #include <asm/fsl_secure_boot.h> 436 437 #endif /* __LS1088A_QDS_H */ 438