1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_QDS_H 8 #define __LS1088A_QDS_H 9 10 #include "ls1088a_common.h" 11 12 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 16 #ifndef __ASSEMBLY__ 17 unsigned long get_board_sys_clk(void); 18 unsigned long get_board_ddr_clk(void); 19 #endif 20 21 22 #if defined(CONFIG_QSPI_BOOT) 23 #define CONFIG_ENV_IS_IN_SPI_FLASH 24 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 25 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 26 #define CONFIG_ENV_SECT_SIZE 0x40000 27 #else 28 #define CONFIG_ENV_IS_IN_FLASH 29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 30 #define CONFIG_ENV_SECT_SIZE 0x20000 31 #define CONFIG_ENV_SIZE 0x20000 32 #endif 33 34 #if defined(CONFIG_QSPI_BOOT) 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #define SYS_NO_FLASH 37 38 #undef CONFIG_CMD_IMLS 39 #define CONFIG_SYS_CLK_FREQ 100000000 40 #define CONFIG_DDR_CLK_FREQ 100000000 41 #else 42 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 43 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 44 #endif 45 46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 47 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 48 49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 50 51 #define CONFIG_DDR_SPD 52 #define CONFIG_DDR_ECC 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 54 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 55 #define SPD_EEPROM_ADDRESS 0x51 56 #define CONFIG_SYS_SPD_BUS_NUM 0 57 58 59 /* 60 * IFC Definitions 61 */ 62 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 63 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 65 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 66 67 #define CONFIG_SYS_NOR0_CSPR \ 68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 69 CSPR_PORT_SIZE_16 | \ 70 CSPR_MSEL_NOR | \ 71 CSPR_V) 72 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 74 CSPR_PORT_SIZE_16 | \ 75 CSPR_MSEL_NOR | \ 76 CSPR_V) 77 #define CONFIG_SYS_NOR1_CSPR \ 78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 79 CSPR_PORT_SIZE_16 | \ 80 CSPR_MSEL_NOR | \ 81 CSPR_V) 82 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 84 CSPR_PORT_SIZE_16 | \ 85 CSPR_MSEL_NOR | \ 86 CSPR_V) 87 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 88 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 89 FTIM0_NOR_TEADC(0x5) | \ 90 FTIM0_NOR_TEAHC(0x5)) 91 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 92 FTIM1_NOR_TRAD_NOR(0x1a) |\ 93 FTIM1_NOR_TSEQRAD_NOR(0x13)) 94 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 95 FTIM2_NOR_TCH(0x4) | \ 96 FTIM2_NOR_TWPH(0x0E) | \ 97 FTIM2_NOR_TWP(0x1c)) 98 #define CONFIG_SYS_NOR_FTIM3 0x04000000 99 #define CONFIG_SYS_IFC_CCR 0x01000000 100 101 #ifndef SYS_NO_FLASH 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 #define CONFIG_SYS_FLASH_QUIET_TEST 106 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 107 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 110 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 112 113 #define CONFIG_SYS_FLASH_EMPTY_INFO 114 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 115 CONFIG_SYS_FLASH_BASE + 0x40000000} 116 #endif 117 #endif 118 119 #define CONFIG_NAND_FSL_IFC 120 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 121 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 122 123 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 125 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 126 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 127 | CSPR_V) 128 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 129 130 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 131 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 132 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 133 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 134 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 135 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 136 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 137 138 #define CONFIG_SYS_NAND_ONFI_DETECTION 139 140 /* ONFI NAND Flash mode0 Timing Params */ 141 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 142 FTIM0_NAND_TWP(0x18) | \ 143 FTIM0_NAND_TWCHT(0x07) | \ 144 FTIM0_NAND_TWH(0x0a)) 145 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 146 FTIM1_NAND_TWBE(0x39) | \ 147 FTIM1_NAND_TRR(0x0e) | \ 148 FTIM1_NAND_TRP(0x18)) 149 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 150 FTIM2_NAND_TREH(0x0a) | \ 151 FTIM2_NAND_TWHRE(0x1e)) 152 #define CONFIG_SYS_NAND_FTIM3 0x0 153 154 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 155 #define CONFIG_SYS_MAX_NAND_DEVICE 1 156 #define CONFIG_MTD_NAND_VERIFY_WRITE 157 #define CONFIG_CMD_NAND 158 159 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 160 161 #define CONFIG_FSL_QIXIS 162 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 163 #define QIXIS_LBMAP_SWITCH 6 164 #define QIXIS_QMAP_MASK 0xe0 165 #define QIXIS_QMAP_SHIFT 5 166 #define QIXIS_LBMAP_MASK 0x0f 167 #define QIXIS_LBMAP_SHIFT 0 168 #define QIXIS_LBMAP_DFLTBANK 0x0e 169 #define QIXIS_LBMAP_ALTBANK 0x2e 170 #define QIXIS_LBMAP_SD 0x00 171 #define QIXIS_LBMAP_SD_QSPI 0x0e 172 #define QIXIS_LBMAP_QSPI 0x0e 173 #define QIXIS_RCW_SRC_SD 0x40 174 #define QIXIS_RCW_SRC_QSPI 0x62 175 #define QIXIS_RST_CTL_RESET 0x41 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 179 #define QIXIS_RST_FORCE_MEM 0x01 180 #define QIXIS_STAT_PRES1 0xb 181 #define QIXIS_SDID_MASK 0x07 182 #define QIXIS_ESDHC_NO_ADAPTER 0x7 183 184 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 185 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 186 | CSPR_PORT_SIZE_8 \ 187 | CSPR_MSEL_GPCM \ 188 | CSPR_V) 189 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 190 | CSPR_PORT_SIZE_8 \ 191 | CSPR_MSEL_GPCM \ 192 | CSPR_V) 193 194 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 195 #if defined(CONFIG_QSPI_BOOT) 196 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 197 #else 198 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 199 #endif 200 /* QIXIS Timing parameters*/ 201 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 202 FTIM0_GPCM_TEADC(0x0e) | \ 203 FTIM0_GPCM_TEAHC(0x0e)) 204 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 205 FTIM1_GPCM_TRAD(0x3f)) 206 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 207 FTIM2_GPCM_TCH(0xf) | \ 208 FTIM2_GPCM_TWP(0x3E)) 209 #define SYS_FPGA_CS_FTIM3 0x0 210 211 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 212 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 213 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 214 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 215 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 216 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 217 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 218 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 219 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 220 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 221 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 222 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 223 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 224 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 225 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 226 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 227 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 228 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 229 #else 230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 232 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 233 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 234 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 235 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 236 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 237 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 238 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 239 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 240 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 241 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 242 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 243 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 244 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 245 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 246 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 247 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 248 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 249 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 250 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 251 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 252 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 253 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 254 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 255 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 256 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 257 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 258 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 259 #define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL 260 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 261 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 262 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 263 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 264 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 265 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 266 #endif 267 268 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 269 270 /* 271 * I2C bus multiplexer 272 */ 273 #define I2C_MUX_PCA_ADDR_PRI 0x77 274 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 275 #define I2C_RETIMER_ADDR 0x18 276 #define I2C_RETIMER_ADDR2 0x19 277 #define I2C_MUX_CH_DEFAULT 0x8 278 #define I2C_MUX_CH5 0xD 279 280 /* 281 * RTC configuration 282 */ 283 #define RTC 284 #define CONFIG_RTC_PCF8563 1 285 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 286 #define CONFIG_CMD_DATE 287 288 /* EEPROM */ 289 #define CONFIG_ID_EEPROM 290 #define CONFIG_SYS_I2C_EEPROM_NXID 291 #define CONFIG_SYS_EEPROM_BUS_NUM 0 292 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 293 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 295 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 296 297 /* QSPI device */ 298 #if defined(CONFIG_QSPI_BOOT) 299 #define CONFIG_FSL_QSPI 300 #define CONFIG_SPI_FLASH_SPANSION 301 #define FSL_QSPI_FLASH_SIZE (1 << 26) 302 #define FSL_QSPI_FLASH_NUM 2 303 304 #endif 305 306 #ifdef CONFIG_FSL_DSPI 307 #define CONFIG_SPI_FLASH_STMICRO 308 #define CONFIG_SPI_FLASH_SST 309 #define CONFIG_SPI_FLASH_EON 310 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 311 #define CONFIG_SF_DEFAULT_BUS 1 312 #define CONFIG_SF_DEFAULT_CS 0 313 #endif 314 #endif 315 316 #define CONFIG_CMD_MEMINFO 317 #define CONFIG_CMD_MEMTEST 318 #define CONFIG_SYS_MEMTEST_START 0x80000000 319 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 320 321 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 322 323 #define CONFIG_FSL_MEMAC 324 325 /* MMC */ 326 #define CONFIG_FSL_ESDHC 327 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 328 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 329 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 330 331 /* Initial environment variables */ 332 #if defined(CONFIG_QSPI_BOOT) 333 #undef CONFIG_EXTRA_ENV_SETTINGS 334 #define CONFIG_EXTRA_ENV_SETTINGS \ 335 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 336 "loadaddr=0x90100000\0" \ 337 "kernel_addr=0x100000\0" \ 338 "ramdisk_addr=0x800000\0" \ 339 "ramdisk_size=0x2000000\0" \ 340 "fdt_high=0xa0000000\0" \ 341 "initrd_high=0xffffffffffffffff\0" \ 342 "kernel_start=0x1000000\0" \ 343 "kernel_load=0xa0000000\0" \ 344 "kernel_size=0x2800000\0" \ 345 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 346 "sf read 0x80100000 0xE00000 0x100000;" \ 347 "fsl_mc start mc 0x80000000 0x80100000\0" \ 348 "mcmemsize=0x70000000 \0" 349 #else /* NOR BOOT */ 350 #undef CONFIG_EXTRA_ENV_SETTINGS 351 #define CONFIG_EXTRA_ENV_SETTINGS \ 352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 353 "loadaddr=0x90100000\0" \ 354 "kernel_addr=0x100000\0" \ 355 "ramdisk_addr=0x800000\0" \ 356 "ramdisk_size=0x2000000\0" \ 357 "fdt_high=0xa0000000\0" \ 358 "initrd_high=0xffffffffffffffff\0" \ 359 "kernel_start=0x1000000\0" \ 360 "kernel_load=0xa0000000\0" \ 361 "kernel_size=0x2800000\0" \ 362 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 363 "mcmemsize=0x70000000 \0" 364 #endif 365 366 #ifdef CONFIG_FSL_MC_ENET 367 #define CONFIG_FSL_MEMAC 368 #define CONFIG_PHYLIB 369 #define CONFIG_PHYLIB_10G 370 #define CONFIG_PHY_VITESSE 371 #define CONFIG_PHY_REALTEK 372 #define CONFIG_PHY_TERANETICS 373 #define RGMII_PHY1_ADDR 0x1 374 #define RGMII_PHY2_ADDR 0x2 375 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 376 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 377 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 378 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 379 380 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 381 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 382 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 383 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 384 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 385 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 386 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 387 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 388 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 389 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 390 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 391 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 392 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 393 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 394 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 395 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 396 397 #define CONFIG_MII /* MII PHY management */ 398 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 399 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 400 401 #endif 402 403 #undef CONFIG_CMDLINE_EDITING 404 #include <config_distro_defaults.h> 405 #define BOOT_TARGET_DEVICES(func) \ 406 func(USB, usb, 0) \ 407 func(MMC, mmc, 0) \ 408 func(SCSI, scsi, 0) \ 409 func(DHCP, dhcp, na) 410 #include <config_distro_bootcmd.h> 411 412 #include <asm/fsl_secure_boot.h> 413 414 #endif /* __LS1088A_QDS_H */ 415