1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088A_QDS_H 8 #define __LS1088A_QDS_H 9 10 #include "ls1088a_common.h" 11 12 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 16 #ifndef __ASSEMBLY__ 17 unsigned long get_board_sys_clk(void); 18 unsigned long get_board_ddr_clk(void); 19 #endif 20 21 22 #if defined(CONFIG_QSPI_BOOT) 23 #define CONFIG_ENV_IS_IN_SPI_FLASH 24 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 25 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 26 #define CONFIG_ENV_SECT_SIZE 0x40000 27 #else 28 #define CONFIG_ENV_IS_IN_FLASH 29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 30 #define CONFIG_ENV_SECT_SIZE 0x20000 31 #define CONFIG_ENV_SIZE 0x20000 32 #endif 33 34 #if defined(CONFIG_QSPI_BOOT) 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #define SYS_NO_FLASH 37 38 #define CONFIG_SYS_CLK_FREQ 100000000 39 #define CONFIG_DDR_CLK_FREQ 100000000 40 #else 41 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 42 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 43 #endif 44 45 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 46 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 47 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 49 50 #define CONFIG_DDR_SPD 51 #define CONFIG_DDR_ECC 52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 53 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 54 #define SPD_EEPROM_ADDRESS 0x51 55 #define CONFIG_SYS_SPD_BUS_NUM 0 56 57 58 /* 59 * IFC Definitions 60 */ 61 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 62 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 64 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 65 66 #define CONFIG_SYS_NOR0_CSPR \ 67 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 68 CSPR_PORT_SIZE_16 | \ 69 CSPR_MSEL_NOR | \ 70 CSPR_V) 71 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 72 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 73 CSPR_PORT_SIZE_16 | \ 74 CSPR_MSEL_NOR | \ 75 CSPR_V) 76 #define CONFIG_SYS_NOR1_CSPR \ 77 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 78 CSPR_PORT_SIZE_16 | \ 79 CSPR_MSEL_NOR | \ 80 CSPR_V) 81 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 82 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 83 CSPR_PORT_SIZE_16 | \ 84 CSPR_MSEL_NOR | \ 85 CSPR_V) 86 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 88 FTIM0_NOR_TEADC(0x5) | \ 89 FTIM0_NOR_TEAHC(0x5)) 90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 91 FTIM1_NOR_TRAD_NOR(0x1a) |\ 92 FTIM1_NOR_TSEQRAD_NOR(0x13)) 93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 94 FTIM2_NOR_TCH(0x4) | \ 95 FTIM2_NOR_TWPH(0x0E) | \ 96 FTIM2_NOR_TWP(0x1c)) 97 #define CONFIG_SYS_NOR_FTIM3 0x04000000 98 #define CONFIG_SYS_IFC_CCR 0x01000000 99 100 #ifndef SYS_NO_FLASH 101 #define CONFIG_FLASH_CFI_DRIVER 102 #define CONFIG_SYS_FLASH_CFI 103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104 #define CONFIG_SYS_FLASH_QUIET_TEST 105 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 106 107 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 109 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 110 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 111 112 #define CONFIG_SYS_FLASH_EMPTY_INFO 113 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 114 CONFIG_SYS_FLASH_BASE + 0x40000000} 115 #endif 116 #endif 117 118 #define CONFIG_NAND_FSL_IFC 119 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 120 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 121 122 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 123 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 124 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 125 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 126 | CSPR_V) 127 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 128 129 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 130 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 131 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 132 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 133 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 134 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 135 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 136 137 #define CONFIG_SYS_NAND_ONFI_DETECTION 138 139 /* ONFI NAND Flash mode0 Timing Params */ 140 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 141 FTIM0_NAND_TWP(0x18) | \ 142 FTIM0_NAND_TWCHT(0x07) | \ 143 FTIM0_NAND_TWH(0x0a)) 144 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 145 FTIM1_NAND_TWBE(0x39) | \ 146 FTIM1_NAND_TRR(0x0e) | \ 147 FTIM1_NAND_TRP(0x18)) 148 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 149 FTIM2_NAND_TREH(0x0a) | \ 150 FTIM2_NAND_TWHRE(0x1e)) 151 #define CONFIG_SYS_NAND_FTIM3 0x0 152 153 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 154 #define CONFIG_SYS_MAX_NAND_DEVICE 1 155 #define CONFIG_MTD_NAND_VERIFY_WRITE 156 #define CONFIG_CMD_NAND 157 158 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 159 160 #define CONFIG_FSL_QIXIS 161 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 162 #define QIXIS_LBMAP_SWITCH 6 163 #define QIXIS_QMAP_MASK 0xe0 164 #define QIXIS_QMAP_SHIFT 5 165 #define QIXIS_LBMAP_MASK 0x0f 166 #define QIXIS_LBMAP_SHIFT 0 167 #define QIXIS_LBMAP_DFLTBANK 0x0e 168 #define QIXIS_LBMAP_ALTBANK 0x2e 169 #define QIXIS_LBMAP_SD 0x00 170 #define QIXIS_LBMAP_SD_QSPI 0x0e 171 #define QIXIS_LBMAP_QSPI 0x0e 172 #define QIXIS_RCW_SRC_SD 0x40 173 #define QIXIS_RCW_SRC_QSPI 0x62 174 #define QIXIS_RST_CTL_RESET 0x41 175 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 176 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 177 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 178 #define QIXIS_RST_FORCE_MEM 0x01 179 #define QIXIS_STAT_PRES1 0xb 180 #define QIXIS_SDID_MASK 0x07 181 #define QIXIS_ESDHC_NO_ADAPTER 0x7 182 183 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 184 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 185 | CSPR_PORT_SIZE_8 \ 186 | CSPR_MSEL_GPCM \ 187 | CSPR_V) 188 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 189 | CSPR_PORT_SIZE_8 \ 190 | CSPR_MSEL_GPCM \ 191 | CSPR_V) 192 193 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) 194 #if defined(CONFIG_QSPI_BOOT) 195 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 196 #else 197 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 198 #endif 199 /* QIXIS Timing parameters*/ 200 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 201 FTIM0_GPCM_TEADC(0x0e) | \ 202 FTIM0_GPCM_TEAHC(0x0e)) 203 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 204 FTIM1_GPCM_TRAD(0x3f)) 205 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 206 FTIM2_GPCM_TCH(0xf) | \ 207 FTIM2_GPCM_TWP(0x3E)) 208 #define SYS_FPGA_CS_FTIM3 0x0 209 210 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 211 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 212 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 213 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 214 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 215 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 216 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 217 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 218 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 219 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 220 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 221 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 222 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK 223 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 224 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 225 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 226 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 227 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 228 #else 229 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 230 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 231 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 232 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 233 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 234 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 235 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 236 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 237 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 238 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 239 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 240 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 241 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 242 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 243 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 244 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 245 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 246 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 247 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 248 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 249 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 250 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 251 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 252 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 253 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 254 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 255 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 256 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 257 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 258 #define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL 259 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 260 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 261 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0 262 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1 263 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2 264 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3 265 #endif 266 267 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 268 269 /* 270 * I2C bus multiplexer 271 */ 272 #define I2C_MUX_PCA_ADDR_PRI 0x77 273 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 274 #define I2C_RETIMER_ADDR 0x18 275 #define I2C_RETIMER_ADDR2 0x19 276 #define I2C_MUX_CH_DEFAULT 0x8 277 #define I2C_MUX_CH5 0xD 278 279 /* 280 * RTC configuration 281 */ 282 #define RTC 283 #define CONFIG_RTC_PCF8563 1 284 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 285 #define CONFIG_CMD_DATE 286 287 /* EEPROM */ 288 #define CONFIG_ID_EEPROM 289 #define CONFIG_SYS_I2C_EEPROM_NXID 290 #define CONFIG_SYS_EEPROM_BUS_NUM 0 291 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 292 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 293 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 295 296 /* QSPI device */ 297 #if defined(CONFIG_QSPI_BOOT) 298 #define CONFIG_FSL_QSPI 299 #define CONFIG_SPI_FLASH_SPANSION 300 #define FSL_QSPI_FLASH_SIZE (1 << 26) 301 #define FSL_QSPI_FLASH_NUM 2 302 303 #endif 304 305 #ifdef CONFIG_FSL_DSPI 306 #define CONFIG_SPI_FLASH_STMICRO 307 #define CONFIG_SPI_FLASH_SST 308 #define CONFIG_SPI_FLASH_EON 309 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 310 #define CONFIG_SF_DEFAULT_BUS 1 311 #define CONFIG_SF_DEFAULT_CS 0 312 #endif 313 #endif 314 315 #define CONFIG_CMD_MEMINFO 316 #define CONFIG_CMD_MEMTEST 317 #define CONFIG_SYS_MEMTEST_START 0x80000000 318 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 319 320 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 321 322 #define CONFIG_FSL_MEMAC 323 324 /* MMC */ 325 #define CONFIG_FSL_ESDHC 326 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 327 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 328 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 329 330 /* Initial environment variables */ 331 #if defined(CONFIG_QSPI_BOOT) 332 #undef CONFIG_EXTRA_ENV_SETTINGS 333 #define CONFIG_EXTRA_ENV_SETTINGS \ 334 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 335 "loadaddr=0x90100000\0" \ 336 "kernel_addr=0x100000\0" \ 337 "ramdisk_addr=0x800000\0" \ 338 "ramdisk_size=0x2000000\0" \ 339 "fdt_high=0xa0000000\0" \ 340 "initrd_high=0xffffffffffffffff\0" \ 341 "kernel_start=0x1000000\0" \ 342 "kernel_load=0xa0000000\0" \ 343 "kernel_size=0x2800000\0" \ 344 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 345 "sf read 0x80100000 0xE00000 0x100000;" \ 346 "fsl_mc start mc 0x80000000 0x80100000\0" \ 347 "mcmemsize=0x70000000 \0" 348 #else /* NOR BOOT */ 349 #undef CONFIG_EXTRA_ENV_SETTINGS 350 #define CONFIG_EXTRA_ENV_SETTINGS \ 351 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 352 "loadaddr=0x90100000\0" \ 353 "kernel_addr=0x100000\0" \ 354 "ramdisk_addr=0x800000\0" \ 355 "ramdisk_size=0x2000000\0" \ 356 "fdt_high=0xa0000000\0" \ 357 "initrd_high=0xffffffffffffffff\0" \ 358 "kernel_start=0x1000000\0" \ 359 "kernel_load=0xa0000000\0" \ 360 "kernel_size=0x2800000\0" \ 361 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 362 "mcmemsize=0x70000000 \0" 363 #endif 364 365 #ifdef CONFIG_FSL_MC_ENET 366 #define CONFIG_FSL_MEMAC 367 #define CONFIG_PHYLIB 368 #define CONFIG_PHYLIB_10G 369 #define CONFIG_PHY_VITESSE 370 #define CONFIG_PHY_REALTEK 371 #define CONFIG_PHY_TERANETICS 372 #define RGMII_PHY1_ADDR 0x1 373 #define RGMII_PHY2_ADDR 0x2 374 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 375 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 376 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 377 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 378 379 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 380 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 381 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 382 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 383 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 384 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 385 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 386 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 387 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 388 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 389 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 390 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 391 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 392 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 393 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 394 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 395 396 #define CONFIG_MII /* MII PHY management */ 397 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 398 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 399 400 #endif 401 402 #undef CONFIG_CMDLINE_EDITING 403 #include <config_distro_defaults.h> 404 #define BOOT_TARGET_DEVICES(func) \ 405 func(USB, usb, 0) \ 406 func(MMC, mmc, 0) \ 407 func(SCSI, scsi, 0) \ 408 func(DHCP, dhcp, na) 409 #include <config_distro_bootcmd.h> 410 411 #include <asm/fsl_secure_boot.h> 412 413 #endif /* __LS1088A_QDS_H */ 414