1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017-2018 NXP 4 */ 5 6 #ifndef __LS1088_COMMON_H 7 #define __LS1088_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_BOARDINFO 12 #define SPL_NO_QIXIS 13 #define SPL_NO_PCI 14 #define SPL_NO_ENV 15 #define SPL_NO_RTC 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #define SPL_NO_QSPI 19 #define SPL_NO_IFC 20 #undef CONFIG_DISPLAY_CPUINFO 21 #endif 22 23 #define CONFIG_REMAKE_ELF 24 #define CONFIG_FSL_LAYERSCAPE 25 26 #include <asm/arch/stream_id_lsch3.h> 27 #include <asm/arch/config.h> 28 #include <asm/arch/soc.h> 29 30 #define LS1088ARDB_PB_BOARD 0x4A 31 /* Link Definitions */ 32 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 33 34 /* Link Definitions */ 35 36 #ifdef CONFIG_QSPI_BOOT 37 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 38 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 39 #define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ 40 CONFIG_ENV_OFFSET) 41 #endif 42 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 45 #if !defined(CONFIG_SD_BOOT) 46 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 47 #endif 48 49 #define CONFIG_VERY_BIG_RAM 50 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 51 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 52 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 53 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 54 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 55 /* 56 * SMP Definitinos 57 */ 58 #define CPU_RELEASE_ADDR secondary_boot_func 59 60 #ifdef CONFIG_PCI 61 #define CONFIG_CMD_PCI 62 #endif 63 64 /* Size of malloc() pool */ 65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 66 67 /* I2C */ 68 #define CONFIG_SYS_I2C 69 70 /* Serial Port */ 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE 1 73 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 74 75 #define CONFIG_BAUDRATE 115200 76 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 77 78 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) 79 /* IFC */ 80 #define CONFIG_FSL_IFC 81 #endif 82 83 /* 84 * During booting, IFC is mapped at the region of 0x30000000. 85 * But this region is limited to 256MB. To accommodate NOR, promjet 86 * and FPGA. This region is divided as below: 87 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 88 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 89 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 90 * 91 * To accommodate bigger NOR flash and other devices, we will map IFC 92 * chip selects to as below: 93 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 94 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 95 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 96 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 97 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 98 * 99 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 100 * CONFIG_SYS_FLASH_BASE has the final address (core view) 101 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 102 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 103 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 104 */ 105 106 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 107 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 108 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 109 110 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 111 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 112 113 #ifndef __ASSEMBLY__ 114 unsigned long long get_qixis_addr(void); 115 #endif 116 117 #define QIXIS_BASE get_qixis_addr() 118 #define QIXIS_BASE_PHYS 0x20000000 119 #define QIXIS_BASE_PHYS_EARLY 0xC000000 120 121 122 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 123 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 124 125 126 /* MC firmware */ 127 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 128 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 129 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 130 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 131 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 132 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 133 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 134 135 /* Define phy_reset function to boot the MC based on mcinitcmd. 136 * This happens late enough to properly fixup u-boot env MAC addresses. 137 */ 138 #define CONFIG_RESET_PHY_R 139 140 /* 141 * Carve out a DDR region which will not be used by u-boot/Linux 142 * 143 * It will be used by MC and Debug Server. The MC region must be 144 * 512MB aligned, so the min size to hide is 512MB. 145 */ 146 147 #if defined(CONFIG_FSL_MC_ENET) 148 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 149 #endif 150 /* Command line configuration */ 151 #define CONFIG_CMD_CACHE 152 153 /* Miscellaneous configurable options */ 154 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 155 156 /* SATA */ 157 #ifdef CONFIG_SCSI 158 #define CONFIG_SCSI_AHCI_PLAT 159 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 160 161 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 162 #define CONFIG_SYS_SCSI_MAX_LUN 1 163 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 164 CONFIG_SYS_SCSI_MAX_LUN) 165 #endif 166 167 /* Physical Memory Map */ 168 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 169 170 #define CONFIG_HWCONFIG 171 #define HWCONFIG_BUFFER_SIZE 128 172 173 /* #define CONFIG_DISPLAY_CPUINFO */ 174 175 #ifndef SPL_NO_ENV 176 /* Allow to overwrite serial and ethaddr */ 177 #define CONFIG_ENV_OVERWRITE 178 179 /* Initial environment variables */ 180 #define CONFIG_EXTRA_ENV_SETTINGS \ 181 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 182 "loadaddr=0x80100000\0" \ 183 "kernel_addr=0x100000\0" \ 184 "ramdisk_addr=0x800000\0" \ 185 "ramdisk_size=0x2000000\0" \ 186 "fdt_high=0xa0000000\0" \ 187 "initrd_high=0xffffffffffffffff\0" \ 188 "kernel_start=0x581000000\0" \ 189 "kernel_load=0xa0000000\0" \ 190 "kernel_size=0x2800000\0" \ 191 "console=ttyAMA0,38400n8\0" \ 192 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 193 " 0x580e00000 \0" 194 195 #if defined(CONFIG_QSPI_BOOT) 196 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ 197 "sf read 0x80001000 0xd00000 0x100000;"\ 198 " fsl_mc lazyapply dpl 0x80001000 &&" \ 199 " sf read $kernel_load $kernel_start" \ 200 " $kernel_size && bootm $kernel_load" 201 #elif defined(CONFIG_SD_BOOT) 202 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ 203 " fsl_mc lazyapply dpl 0x80001000 &&" \ 204 " mmc read $kernel_load $kernel_start" \ 205 " $kernel_size && bootm $kernel_load" 206 #else /* NOR BOOT*/ 207 #define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ 208 " cp.b $kernel_start $kernel_load" \ 209 " $kernel_size && bootm $kernel_load" 210 #endif 211 #endif 212 213 /* Monitor Command Prompt */ 214 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 215 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 216 sizeof(CONFIG_SYS_PROMPT) + 16) 217 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 218 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 219 220 #ifdef CONFIG_SPL 221 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 222 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 223 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 224 #define CONFIG_SPL_MAX_SIZE 0x16000 225 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 226 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 227 #define CONFIG_SPL_TEXT_BASE 0x1800a000 228 229 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 230 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 231 232 #ifdef CONFIG_SECURE_BOOT 233 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 234 /* 235 * HDR would be appended at end of image and copied to DDR along 236 * with U-Boot image. Here u-boot max. size is 512K. So if binary 237 * size increases then increase this size in case of secure boot as 238 * it uses raw u-boot image instead of fit image. 239 */ 240 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 241 #else 242 #define CONFIG_SYS_MONITOR_LEN 0x100000 243 #endif /* ifdef CONFIG_SECURE_BOOT */ 244 245 #endif 246 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 247 248 #endif /* __LS1088_COMMON_H */ 249