1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088_COMMON_H 8 #define __LS1088_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_BOARDINFO 13 #define SPL_NO_QIXIS 14 #define SPL_NO_PCI 15 #define SPL_NO_ENV 16 #define SPL_NO_RTC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QSPI 20 #define SPL_NO_IFC 21 #undef CONFIG_DISPLAY_CPUINFO 22 #endif 23 24 #define CONFIG_REMAKE_ELF 25 #define CONFIG_FSL_LAYERSCAPE 26 #define CONFIG_MP 27 28 #include <asm/arch/stream_id_lsch3.h> 29 #include <asm/arch/config.h> 30 #include <asm/arch/soc.h> 31 32 /* Link Definitions */ 33 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 34 35 /* Link Definitions */ 36 37 #ifdef CONFIG_QSPI_BOOT 38 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 39 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 40 #define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ 41 CONFIG_ENV_OFFSET) 42 #endif 43 44 #define CONFIG_SKIP_LOWLEVEL_INIT 45 46 #if !defined(CONFIG_SD_BOOT) 47 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 48 #endif 49 50 #define CONFIG_VERY_BIG_RAM 51 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 52 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 54 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 55 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 56 /* 57 * SMP Definitinos 58 */ 59 #define CPU_RELEASE_ADDR secondary_boot_func 60 61 #ifdef CONFIG_PCI 62 #define CONFIG_CMD_PCI 63 #endif 64 65 /* Size of malloc() pool */ 66 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 67 68 /* I2C */ 69 #define CONFIG_SYS_I2C 70 #define CONFIG_SYS_I2C_MXC 71 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 72 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 73 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 74 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 75 76 /* Serial Port */ 77 #define CONFIG_CONS_INDEX 1 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE 1 80 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 81 82 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 84 85 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) 86 /* IFC */ 87 #define CONFIG_FSL_IFC 88 #endif 89 90 /* 91 * During booting, IFC is mapped at the region of 0x30000000. 92 * But this region is limited to 256MB. To accommodate NOR, promjet 93 * and FPGA. This region is divided as below: 94 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 95 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 96 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 97 * 98 * To accommodate bigger NOR flash and other devices, we will map IFC 99 * chip selects to as below: 100 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 101 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 102 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 103 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 104 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 105 * 106 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 107 * CONFIG_SYS_FLASH_BASE has the final address (core view) 108 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 109 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 110 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 111 */ 112 113 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 114 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 115 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 116 117 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 118 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 119 120 #ifndef __ASSEMBLY__ 121 unsigned long long get_qixis_addr(void); 122 #endif 123 124 #define QIXIS_BASE get_qixis_addr() 125 #define QIXIS_BASE_PHYS 0x20000000 126 #define QIXIS_BASE_PHYS_EARLY 0xC000000 127 128 129 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 130 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 131 132 133 /* MC firmware */ 134 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 135 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 136 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 137 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 138 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 139 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 140 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 141 142 /* Define phy_reset function to boot the MC based on mcinitcmd. 143 * This happens late enough to properly fixup u-boot env MAC addresses. 144 */ 145 #define CONFIG_RESET_PHY_R 146 147 /* 148 * Carve out a DDR region which will not be used by u-boot/Linux 149 * 150 * It will be used by MC and Debug Server. The MC region must be 151 * 512MB aligned, so the min size to hide is 512MB. 152 */ 153 154 #if defined(CONFIG_FSL_MC_ENET) 155 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 156 #endif 157 /* Command line configuration */ 158 #define CONFIG_CMD_GREPENV 159 #define CONFIG_CMD_CACHE 160 161 /* Miscellaneous configurable options */ 162 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 163 164 /* SATA */ 165 #ifdef CONFIG_SCSI 166 #define CONFIG_SCSI_AHCI_PLAT 167 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 168 169 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 170 #define CONFIG_SYS_SCSI_MAX_LUN 1 171 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 172 CONFIG_SYS_SCSI_MAX_LUN) 173 #endif 174 175 /* Physical Memory Map */ 176 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 177 178 #define CONFIG_NR_DRAM_BANKS 2 179 180 #define CONFIG_HWCONFIG 181 #define HWCONFIG_BUFFER_SIZE 128 182 183 /* #define CONFIG_DISPLAY_CPUINFO */ 184 185 #ifndef SPL_NO_ENV 186 /* Allow to overwrite serial and ethaddr */ 187 #define CONFIG_ENV_OVERWRITE 188 189 /* Initial environment variables */ 190 #define CONFIG_EXTRA_ENV_SETTINGS \ 191 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 192 "loadaddr=0x80100000\0" \ 193 "kernel_addr=0x100000\0" \ 194 "ramdisk_addr=0x800000\0" \ 195 "ramdisk_size=0x2000000\0" \ 196 "fdt_high=0xa0000000\0" \ 197 "initrd_high=0xffffffffffffffff\0" \ 198 "kernel_start=0x581000000\0" \ 199 "kernel_load=0xa0000000\0" \ 200 "kernel_size=0x2800000\0" \ 201 "console=ttyAMA0,38400n8\0" \ 202 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 203 " 0x580e00000 \0" 204 205 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 206 "earlycon=uart8250,mmio,0x21c0500 " \ 207 "ramdisk_size=0x3000000 default_hugepagesz=2m" \ 208 " hugepagesz=2m hugepages=256" 209 #if defined(CONFIG_QSPI_BOOT) 210 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ 211 "sf read 0x80200000 0xd00000 0x100000;"\ 212 " fsl_mc apply dpl 0x80200000 &&" \ 213 " sf read $kernel_load $kernel_start" \ 214 " $kernel_size && bootm $kernel_load" 215 #elif defined(CONFIG_SD_BOOT) 216 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\ 217 " fsl_mc apply dpl 0x80200000 &&" \ 218 " mmc read $kernel_load $kernel_start" \ 219 " $kernel_size && bootm $kernel_load" 220 #else /* NOR BOOT*/ 221 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 222 " cp.b $kernel_start $kernel_load" \ 223 " $kernel_size && bootm $kernel_load" 224 #endif 225 #endif 226 227 /* Monitor Command Prompt */ 228 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 230 sizeof(CONFIG_SYS_PROMPT) + 16) 231 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 232 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 233 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 234 235 #ifdef CONFIG_SPL 236 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 237 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 238 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 239 #define CONFIG_SPL_MAX_SIZE 0x16000 240 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 241 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 242 #define CONFIG_SPL_TEXT_BASE 0x1800a000 243 244 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 245 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 246 247 #ifdef CONFIG_SECURE_BOOT 248 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 249 /* 250 * HDR would be appended at end of image and copied to DDR along 251 * with U-Boot image. Here u-boot max. size is 512K. So if binary 252 * size increases then increase this size in case of secure boot as 253 * it uses raw u-boot image instead of fit image. 254 */ 255 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 256 #else 257 #define CONFIG_SYS_MONITOR_LEN 0x100000 258 #endif /* ifdef CONFIG_SECURE_BOOT */ 259 260 #endif 261 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 262 263 #endif /* __LS1088_COMMON_H */ 264