1 /* 2 * Copyright 2017 NXP 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1088_COMMON_H 8 #define __LS1088_COMMON_H 9 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_MP 14 15 #include <asm/arch/stream_id_lsch3.h> 16 #include <asm/arch/config.h> 17 #include <asm/arch/soc.h> 18 19 /* Link Definitions */ 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 22 /* Link Definitions */ 23 #ifdef CONFIG_SPL 24 #define CONFIG_SYS_TEXT_BASE 0x80400000 25 #else 26 #ifdef CONFIG_QSPI_BOOT 27 #define CONFIG_SYS_TEXT_BASE 0x20100000 28 #else 29 #define CONFIG_SYS_TEXT_BASE 0x30100000 30 #endif 31 #endif 32 33 #define CONFIG_SUPPORT_RAW_INITRD 34 35 36 #define CONFIG_SKIP_LOWLEVEL_INIT 37 38 #if !defined(CONFIG_SD_BOOT) 39 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 40 #endif 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 47 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 48 /* 49 * SMP Definitinos 50 */ 51 #define CPU_RELEASE_ADDR secondary_boot_func 52 53 #ifdef CONFIG_PCI 54 #define CONFIG_CMD_PCI 55 #endif 56 57 /* Size of malloc() pool */ 58 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 59 60 /* I2C */ 61 #define CONFIG_SYS_I2C 62 #define CONFIG_SYS_I2C_MXC 63 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 64 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 65 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 66 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 67 68 /* Serial Port */ 69 #define CONFIG_CONS_INDEX 1 70 #define CONFIG_SYS_NS16550_SERIAL 71 #define CONFIG_SYS_NS16550_REG_SIZE 1 72 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 73 74 #define CONFIG_BAUDRATE 115200 75 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 76 77 /* IFC */ 78 #define CONFIG_FSL_IFC 79 80 /* 81 * During booting, IFC is mapped at the region of 0x30000000. 82 * But this region is limited to 256MB. To accommodate NOR, promjet 83 * and FPGA. This region is divided as below: 84 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 85 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 86 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 87 * 88 * To accommodate bigger NOR flash and other devices, we will map IFC 89 * chip selects to as below: 90 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 91 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 92 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 93 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 94 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 95 * 96 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 97 * CONFIG_SYS_FLASH_BASE has the final address (core view) 98 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 99 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 100 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 101 */ 102 103 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 104 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 105 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 106 107 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 108 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 109 110 #ifndef __ASSEMBLY__ 111 unsigned long long get_qixis_addr(void); 112 #endif 113 114 #define QIXIS_BASE get_qixis_addr() 115 #define QIXIS_BASE_PHYS 0x20000000 116 #define QIXIS_BASE_PHYS_EARLY 0xC000000 117 118 119 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 120 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 121 122 123 /* MC firmware */ 124 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 125 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 126 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 127 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 128 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 129 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 130 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 131 132 /* Define phy_reset function to boot the MC based on mcinitcmd. 133 * This happens late enough to properly fixup u-boot env MAC addresses. 134 */ 135 #define CONFIG_RESET_PHY_R 136 137 /* 138 * Carve out a DDR region which will not be used by u-boot/Linux 139 * 140 * It will be used by MC and Debug Server. The MC region must be 141 * 512MB aligned, so the min size to hide is 512MB. 142 */ 143 144 #if defined(CONFIG_FSL_MC_ENET) 145 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) 146 #endif 147 /* Command line configuration */ 148 #define CONFIG_CMD_GREPENV 149 #define CONFIG_CMD_CACHE 150 151 /* Miscellaneous configurable options */ 152 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 153 154 /* SATA */ 155 #ifdef CONFIG_SCSI 156 #define CONFIG_LIBATA 157 #define CONFIG_SCSI_AHCI_PLAT 158 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 159 160 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 161 #define CONFIG_SYS_SCSI_MAX_LUN 1 162 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 163 CONFIG_SYS_SCSI_MAX_LUN) 164 #endif 165 166 /* Physical Memory Map */ 167 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 168 169 #define CONFIG_NR_DRAM_BANKS 2 170 171 #define CONFIG_HWCONFIG 172 #define HWCONFIG_BUFFER_SIZE 128 173 174 /* #define CONFIG_DISPLAY_CPUINFO */ 175 176 /* Allow to overwrite serial and ethaddr */ 177 #define CONFIG_ENV_OVERWRITE 178 179 /* Initial environment variables */ 180 #define CONFIG_EXTRA_ENV_SETTINGS \ 181 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 182 "loadaddr=0x80100000\0" \ 183 "kernel_addr=0x100000\0" \ 184 "ramdisk_addr=0x800000\0" \ 185 "ramdisk_size=0x2000000\0" \ 186 "fdt_high=0xa0000000\0" \ 187 "initrd_high=0xffffffffffffffff\0" \ 188 "kernel_start=0x581000000\0" \ 189 "kernel_load=0xa0000000\0" \ 190 "kernel_size=0x2800000\0" \ 191 "console=ttyAMA0,38400n8\0" \ 192 "mcinitcmd=fsl_mc start mc 0x580a00000" \ 193 " 0x580e00000 \0" 194 195 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 196 "earlycon=uart8250,mmio,0x21c0500 " \ 197 "ramdisk_size=0x3000000 default_hugepagesz=2m" \ 198 " hugepagesz=2m hugepages=256" 199 #if defined(CONFIG_QSPI_BOOT) 200 #define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ 201 "sf read 0x80200000 0xd00000 0x100000;"\ 202 " fsl_mc apply dpl 0x80200000 &&" \ 203 " sf read $kernel_load $kernel_start" \ 204 " $kernel_size && bootm $kernel_load" 205 #elif defined(CONFIG_SD_BOOT) 206 #define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\ 207 " fsl_mc apply dpl 0x80200000 &&" \ 208 " mmc read $kernel_load $kernel_start" \ 209 " $kernel_size && bootm $kernel_load" 210 #else /* NOR BOOT*/ 211 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ 212 " cp.b $kernel_start $kernel_load" \ 213 " $kernel_size && bootm $kernel_load" 214 #endif 215 216 /* Monitor Command Prompt */ 217 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 218 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 219 sizeof(CONFIG_SYS_PROMPT) + 16) 220 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 221 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 222 #define CONFIG_SYS_LONGHELP 223 #define CONFIG_CMDLINE_EDITING 1 224 #define CONFIG_AUTO_COMPLETE 225 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 226 227 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 228 229 #ifdef CONFIG_SPL 230 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 231 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 232 #define CONFIG_SPL_FRAMEWORK 233 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 234 #define CONFIG_SPL_MAX_SIZE 0x16000 235 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 236 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 237 #define CONFIG_SPL_TEXT_BASE 0x1800a000 238 239 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 240 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 241 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 242 #endif 243 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 244 245 #endif /* __LS1088_COMMON_H */ 246