1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046ARDB_H__ 8 #define __LS1046ARDB_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_FSL_LS_PPA) 13 #define CONFIG_ARMV8_PSCI 14 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT 15 #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) 16 17 #define CONFIG_SYS_LS_PPA_FW_IN_XIP 18 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP 19 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 20 #endif 21 #endif 22 23 #ifdef CONFIG_SD_BOOT 24 #define CONFIG_SYS_TEXT_BASE 0x82000000 25 #else 26 #define CONFIG_SYS_TEXT_BASE 0x40100000 27 #endif 28 29 #define CONFIG_SYS_CLK_FREQ 100000000 30 #define CONFIG_DDR_CLK_FREQ 100000000 31 32 #define CONFIG_LAYERSCAPE_NS_ACCESS 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 36 /* Physical Memory Map */ 37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 38 #define CONFIG_NR_DRAM_BANKS 2 39 40 #define CONFIG_DDR_SPD 41 #define SPD_EEPROM_ADDRESS 0x51 42 #define CONFIG_SYS_SPD_BUS_NUM 0 43 44 #define CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 48 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 49 50 #ifdef CONFIG_RAMBOOT_PBL 51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg 52 #endif 53 54 #ifdef CONFIG_SD_BOOT 55 #ifdef CONFIG_EMMC_BOOT 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 58 #else 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 60 #endif 61 #endif 62 63 /* No NOR flash */ 64 #define CONFIG_SYS_NO_FLASH 65 66 /* IFC */ 67 #define CONFIG_FSL_IFC 68 69 /* 70 * NAND Flash Definitions 71 */ 72 #define CONFIG_NAND_FSL_IFC 73 74 #define CONFIG_SYS_NAND_BASE 0x7e800000 75 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 76 77 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 78 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 79 | CSPR_PORT_SIZE_8 \ 80 | CSPR_MSEL_NAND \ 81 | CSPR_V) 82 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 83 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 84 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 85 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 86 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 87 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 88 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 89 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 90 91 #define CONFIG_SYS_NAND_ONFI_DETECTION 92 93 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 94 FTIM0_NAND_TWP(0x18) | \ 95 FTIM0_NAND_TWCHT(0x7) | \ 96 FTIM0_NAND_TWH(0xa)) 97 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 98 FTIM1_NAND_TWBE(0x39) | \ 99 FTIM1_NAND_TRR(0xe) | \ 100 FTIM1_NAND_TRP(0x18)) 101 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 102 FTIM2_NAND_TREH(0xa) | \ 103 FTIM2_NAND_TWHRE(0x1e)) 104 #define CONFIG_SYS_NAND_FTIM3 0x0 105 106 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 107 #define CONFIG_SYS_MAX_NAND_DEVICE 1 108 #define CONFIG_MTD_NAND_VERIFY_WRITE 109 #define CONFIG_CMD_NAND 110 111 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 112 113 /* 114 * CPLD 115 */ 116 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 117 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 118 119 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 120 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 121 CSPR_PORT_SIZE_8 | \ 122 CSPR_MSEL_GPCM | \ 123 CSPR_V) 124 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 125 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 126 127 /* CPLD Timing parameters for IFC GPCM */ 128 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 129 FTIM0_GPCM_TEADC(0x0e) | \ 130 FTIM0_GPCM_TEAHC(0x0e)) 131 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 132 FTIM1_GPCM_TRAD(0x3f)) 133 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 134 FTIM2_GPCM_TCH(0xf) | \ 135 FTIM2_GPCM_TWP(0x3E)) 136 #define CONFIG_SYS_CPLD_FTIM3 0x0 137 138 /* IFC Timing Params */ 139 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 140 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 141 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 142 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 143 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 144 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 145 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 146 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 147 148 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 149 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 150 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 151 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 152 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 153 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 154 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 155 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 156 157 /* EEPROM */ 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_NXID 160 #define CONFIG_SYS_EEPROM_BUS_NUM 0 161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 163 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 165 #define I2C_RETIMER_ADDR 0x18 166 167 /* 168 * Environment 169 */ 170 #define CONFIG_ENV_OVERWRITE 171 172 #if defined(CONFIG_SD_BOOT) 173 #define CONFIG_ENV_IS_IN_MMC 174 #define CONFIG_SYS_MMC_ENV_DEV 0 175 #define CONFIG_ENV_OFFSET (1024 * 1024) 176 #define CONFIG_ENV_SIZE 0x2000 177 #else 178 #define CONFIG_ENV_IS_IN_SPI_FLASH 179 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 180 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ 181 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 182 #endif 183 184 /* FMan */ 185 #ifdef CONFIG_SYS_DPAA_FMAN 186 #define CONFIG_FMAN_ENET 187 #define CONFIG_PHYLIB 188 #define CONFIG_PHYLIB_10G 189 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 190 191 #define CONFIG_PHY_REALTEK 192 #define CONFIG_PHY_AQUANTIA 193 #define AQR105_IRQ_MASK 0x80000000 194 195 #define RGMII_PHY1_ADDR 0x1 196 #define RGMII_PHY2_ADDR 0x2 197 198 #define SGMII_PHY1_ADDR 0x3 199 #define SGMII_PHY2_ADDR 0x4 200 201 #define FM1_10GEC1_PHY_ADDR 0x0 202 203 #define CONFIG_ETHPRIME "FM1@DTSEC3" 204 #endif 205 206 /* QSPI device */ 207 #ifdef CONFIG_FSL_QSPI 208 #define CONFIG_SPI_FLASH_SPANSION 209 #define FSL_QSPI_FLASH_SIZE (1 << 26) 210 #define FSL_QSPI_FLASH_NUM 2 211 #define CONFIG_SPI_FLASH_BAR 212 #endif 213 214 /* SATA */ 215 #define CONFIG_LIBATA 216 #define CONFIG_SCSI_AHCI 217 #define CONFIG_SCSI_AHCI_PLAT 218 #define CONFIG_SCSI 219 #define CONFIG_DOS_PARTITION 220 #define CONFIG_BOARD_LATE_INIT 221 222 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 223 224 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 225 #define CONFIG_SYS_SCSI_MAX_LUN 1 226 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 227 CONFIG_SYS_SCSI_MAX_LUN) 228 #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ 229 "$kernel_start $kernel_size;" \ 230 "bootm $kernel_load" 231 232 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \ 233 "15m(u-boot),48m(kernel.itb);" \ 234 "7e800000.flash:16m(nand_uboot)," \ 235 "48m(nand_kernel),448m(nand_free)" 236 237 #endif /* __LS1046ARDB_H__ */ 238