1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046ARDB_H__ 8 #define __LS1046ARDB_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_FSL_LS_PPA) 13 #define CONFIG_ARMV8_PSCI 14 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT 15 #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) 16 17 #define CONFIG_SYS_LS_PPA_FW_IN_XIP 18 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP 19 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x40500000 20 #endif 21 #endif 22 23 #define CONFIG_DISPLAY_CPUINFO 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 #ifdef CONFIG_SD_BOOT 27 #define CONFIG_SYS_TEXT_BASE 0x82000000 28 #else 29 #define CONFIG_SYS_TEXT_BASE 0x40100000 30 #endif 31 32 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_DDR_CLK_FREQ 100000000 34 35 #define CONFIG_LAYERSCAPE_NS_ACCESS 36 #define CONFIG_MISC_INIT_R 37 38 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 39 /* Physical Memory Map */ 40 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 41 #define CONFIG_NR_DRAM_BANKS 2 42 43 #define CONFIG_DDR_SPD 44 #define SPD_EEPROM_ADDRESS 0x51 45 #define CONFIG_SYS_SPD_BUS_NUM 0 46 47 #define CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 50 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 51 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 52 53 #ifdef CONFIG_RAMBOOT_PBL 54 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg 55 #endif 56 57 #ifdef CONFIG_SD_BOOT 58 #ifdef CONFIG_EMMC_BOOT 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 61 #else 62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 63 #endif 64 #endif 65 66 /* No NOR flash */ 67 #define CONFIG_SYS_NO_FLASH 68 69 /* IFC */ 70 #define CONFIG_FSL_IFC 71 72 /* 73 * NAND Flash Definitions 74 */ 75 #define CONFIG_NAND_FSL_IFC 76 77 #define CONFIG_SYS_NAND_BASE 0x7e800000 78 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 79 80 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 81 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 82 | CSPR_PORT_SIZE_8 \ 83 | CSPR_MSEL_NAND \ 84 | CSPR_V) 85 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 86 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 87 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 88 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 89 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 90 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 91 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 92 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 93 94 #define CONFIG_SYS_NAND_ONFI_DETECTION 95 96 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 97 FTIM0_NAND_TWP(0x18) | \ 98 FTIM0_NAND_TWCHT(0x7) | \ 99 FTIM0_NAND_TWH(0xa)) 100 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 101 FTIM1_NAND_TWBE(0x39) | \ 102 FTIM1_NAND_TRR(0xe) | \ 103 FTIM1_NAND_TRP(0x18)) 104 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 105 FTIM2_NAND_TREH(0xa) | \ 106 FTIM2_NAND_TWHRE(0x1e)) 107 #define CONFIG_SYS_NAND_FTIM3 0x0 108 109 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 110 #define CONFIG_SYS_MAX_NAND_DEVICE 1 111 #define CONFIG_MTD_NAND_VERIFY_WRITE 112 #define CONFIG_CMD_NAND 113 114 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 115 116 /* 117 * CPLD 118 */ 119 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 120 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 121 122 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 123 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 124 CSPR_PORT_SIZE_8 | \ 125 CSPR_MSEL_GPCM | \ 126 CSPR_V) 127 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 128 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 129 130 /* CPLD Timing parameters for IFC GPCM */ 131 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 132 FTIM0_GPCM_TEADC(0x0e) | \ 133 FTIM0_GPCM_TEAHC(0x0e)) 134 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 135 FTIM1_GPCM_TRAD(0x3f)) 136 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 137 FTIM2_GPCM_TCH(0xf) | \ 138 FTIM2_GPCM_TWP(0x3E)) 139 #define CONFIG_SYS_CPLD_FTIM3 0x0 140 141 /* IFC Timing Params */ 142 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 143 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 144 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 145 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 146 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 147 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 148 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 149 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 150 151 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 152 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 153 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 154 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 155 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 156 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 157 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 158 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 168 #define I2C_RETIMER_ADDR 0x18 169 170 /* 171 * Environment 172 */ 173 #define CONFIG_ENV_OVERWRITE 174 175 #if defined(CONFIG_SD_BOOT) 176 #define CONFIG_ENV_IS_IN_MMC 177 #define CONFIG_SYS_MMC_ENV_DEV 0 178 #define CONFIG_ENV_OFFSET (1024 * 1024) 179 #define CONFIG_ENV_SIZE 0x2000 180 #else 181 #define CONFIG_ENV_IS_IN_SPI_FLASH 182 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 183 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ 184 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 185 #endif 186 187 /* FMan */ 188 #ifdef CONFIG_SYS_DPAA_FMAN 189 #define CONFIG_FMAN_ENET 190 #define CONFIG_PHYLIB 191 #define CONFIG_PHYLIB_10G 192 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 193 194 #define CONFIG_PHY_REALTEK 195 #define CONFIG_PHY_AQUANTIA 196 #define AQR105_IRQ_MASK 0x80000000 197 198 #define RGMII_PHY1_ADDR 0x1 199 #define RGMII_PHY2_ADDR 0x2 200 201 #define SGMII_PHY1_ADDR 0x3 202 #define SGMII_PHY2_ADDR 0x4 203 204 #define FM1_10GEC1_PHY_ADDR 0x0 205 206 #define CONFIG_ETHPRIME "FM1@DTSEC3" 207 #endif 208 209 /* QSPI device */ 210 #ifdef CONFIG_FSL_QSPI 211 #define CONFIG_SPI_FLASH_SPANSION 212 #define FSL_QSPI_FLASH_SIZE (1 << 26) 213 #define FSL_QSPI_FLASH_NUM 2 214 #define CONFIG_SPI_FLASH_BAR 215 #endif 216 217 /* SATA */ 218 #define CONFIG_LIBATA 219 #define CONFIG_SCSI_AHCI 220 #define CONFIG_SCSI_AHCI_PLAT 221 #define CONFIG_SCSI 222 #define CONFIG_DOS_PARTITION 223 #define CONFIG_BOARD_LATE_INIT 224 225 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 226 227 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 228 #define CONFIG_SYS_SCSI_MAX_LUN 1 229 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 230 CONFIG_SYS_SCSI_MAX_LUN) 231 #define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ 232 "$kernel_start $kernel_size;" \ 233 "bootm $kernel_load" 234 235 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \ 236 "15m(u-boot),48m(kernel.itb);" \ 237 "7e800000.flash:16m(nand_uboot)," \ 238 "48m(nand_kernel),448m(nand_free)" 239 240 #endif /* __LS1046ARDB_H__ */ 241