1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40100000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #ifndef CONFIG_SPL 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #endif 44 45 #define CONFIG_DDR_ECC 46 #ifdef CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 51 /* DSPI */ 52 #ifdef CONFIG_FSL_DSPI 53 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 54 #define CONFIG_SPI_FLASH_SST /* cs1 */ 55 #define CONFIG_SPI_FLASH_EON /* cs2 */ 56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 57 #define CONFIG_SF_DEFAULT_BUS 1 58 #define CONFIG_SF_DEFAULT_CS 0 59 #endif 60 #endif 61 62 /* QSPI */ 63 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 64 #ifdef CONFIG_FSL_QSPI 65 #define CONFIG_SPI_FLASH_SPANSION 66 #define FSL_QSPI_FLASH_SIZE (1 << 24) 67 #define FSL_QSPI_FLASH_NUM 2 68 #endif 69 #endif 70 71 #ifdef CONFIG_SYS_DPAA_FMAN 72 #define CONFIG_FMAN_ENET 73 #define CONFIG_PHYLIB 74 #define CONFIG_PHY_VITESSE 75 #define CONFIG_PHY_REALTEK 76 #define CONFIG_PHYLIB_10G 77 #define RGMII_PHY1_ADDR 0x1 78 #define RGMII_PHY2_ADDR 0x2 79 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 80 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 81 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 82 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 83 /* PHY address on QSGMII riser card on slot 2 */ 84 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 85 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 86 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 87 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 88 #endif 89 90 #ifdef CONFIG_RAMBOOT_PBL 91 #define CONFIG_SYS_FSL_PBL_PBI \ 92 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 93 #endif 94 95 #ifdef CONFIG_NAND_BOOT 96 #define CONFIG_SYS_FSL_PBL_RCW \ 97 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 98 #endif 99 100 #ifdef CONFIG_SD_BOOT 101 #ifdef CONFIG_SD_BOOT_QSPI 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 104 #else 105 #define CONFIG_SYS_FSL_PBL_RCW \ 106 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 107 #endif 108 #endif 109 110 /* IFC */ 111 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 112 #define CONFIG_FSL_IFC 113 /* 114 * CONFIG_SYS_FLASH_BASE has the final address (core view) 115 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 116 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 117 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 118 */ 119 #define CONFIG_SYS_FLASH_BASE 0x60000000 120 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 121 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 122 123 #ifdef CONFIG_MTD_NOR_FLASH 124 #define CONFIG_FLASH_CFI_DRIVER 125 #define CONFIG_SYS_FLASH_CFI 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 127 #define CONFIG_SYS_FLASH_QUIET_TEST 128 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 129 #endif 130 #endif 131 132 /* LPUART */ 133 #ifdef CONFIG_LPUART 134 #define CONFIG_LPUART_32B_REG 135 #define CFG_UART_MUX_MASK 0x6 136 #define CFG_UART_MUX_SHIFT 1 137 #define CFG_LPUART_EN 0x2 138 #endif 139 140 /* USB */ 141 #define CONFIG_HAS_FSL_XHCI_USB 142 #ifdef CONFIG_HAS_FSL_XHCI_USB 143 #define CONFIG_USB_XHCI_HCD 144 #define CONFIG_USB_XHCI_FSL 145 #define CONFIG_USB_XHCI_DWC3 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 147 #define CONFIG_USB_STORAGE 148 #endif 149 150 /* SATA */ 151 #define CONFIG_LIBATA 152 #define CONFIG_SCSI_AHCI 153 #define CONFIG_SCSI_AHCI_PLAT 154 155 /* EEPROM */ 156 #define CONFIG_ID_EEPROM 157 #define CONFIG_SYS_I2C_EEPROM_NXID 158 #define CONFIG_SYS_EEPROM_BUS_NUM 0 159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 161 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 162 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 163 164 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 165 166 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 167 #define CONFIG_SYS_SCSI_MAX_LUN 1 168 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 169 CONFIG_SYS_SCSI_MAX_LUN) 170 171 /* 172 * IFC Definitions 173 */ 174 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 175 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 176 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 177 CSPR_PORT_SIZE_16 | \ 178 CSPR_MSEL_NOR | \ 179 CSPR_V) 180 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 181 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 182 + 0x8000000) | \ 183 CSPR_PORT_SIZE_16 | \ 184 CSPR_MSEL_NOR | \ 185 CSPR_V) 186 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 187 188 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 189 CSOR_NOR_TRHZ_80) 190 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 191 FTIM0_NOR_TEADC(0x5) | \ 192 FTIM0_NOR_TEAHC(0x5)) 193 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 194 FTIM1_NOR_TRAD_NOR(0x1a) | \ 195 FTIM1_NOR_TSEQRAD_NOR(0x13)) 196 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 197 FTIM2_NOR_TCH(0x4) | \ 198 FTIM2_NOR_TWPH(0xe) | \ 199 FTIM2_NOR_TWP(0x1c)) 200 #define CONFIG_SYS_NOR_FTIM3 0 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 206 207 #define CONFIG_SYS_FLASH_EMPTY_INFO 208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 209 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 210 211 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 212 #define CONFIG_SYS_WRITE_SWAPPED_DATA 213 214 /* 215 * NAND Flash Definitions 216 */ 217 #define CONFIG_NAND_FSL_IFC 218 219 #define CONFIG_SYS_NAND_BASE 0x7e800000 220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 221 222 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 223 224 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 \ 226 | CSPR_MSEL_NAND \ 227 | CSPR_V) 228 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 230 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 231 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 232 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 233 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 234 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 235 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 236 237 #define CONFIG_SYS_NAND_ONFI_DETECTION 238 239 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 240 FTIM0_NAND_TWP(0x18) | \ 241 FTIM0_NAND_TWCHT(0x7) | \ 242 FTIM0_NAND_TWH(0xa)) 243 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 244 FTIM1_NAND_TWBE(0x39) | \ 245 FTIM1_NAND_TRR(0xe) | \ 246 FTIM1_NAND_TRP(0x18)) 247 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 248 FTIM2_NAND_TREH(0xa) | \ 249 FTIM2_NAND_TWHRE(0x1e)) 250 #define CONFIG_SYS_NAND_FTIM3 0x0 251 252 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 253 #define CONFIG_SYS_MAX_NAND_DEVICE 1 254 #define CONFIG_MTD_NAND_VERIFY_WRITE 255 256 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 257 #endif 258 259 #ifdef CONFIG_NAND_BOOT 260 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 261 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 262 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 263 #endif 264 265 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 266 #define CONFIG_QIXIS_I2C_ACCESS 267 #define CONFIG_SYS_I2C_EARLY_INIT 268 #endif 269 270 /* 271 * QIXIS Definitions 272 */ 273 #define CONFIG_FSL_QIXIS 274 275 #ifdef CONFIG_FSL_QIXIS 276 #define QIXIS_BASE 0x7fb00000 277 #define QIXIS_BASE_PHYS QIXIS_BASE 278 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 279 #define QIXIS_LBMAP_SWITCH 6 280 #define QIXIS_LBMAP_MASK 0x0f 281 #define QIXIS_LBMAP_SHIFT 0 282 #define QIXIS_LBMAP_DFLTBANK 0x00 283 #define QIXIS_LBMAP_ALTBANK 0x04 284 #define QIXIS_LBMAP_NAND 0x09 285 #define QIXIS_LBMAP_SD 0x00 286 #define QIXIS_LBMAP_SD_QSPI 0xff 287 #define QIXIS_LBMAP_QSPI 0xff 288 #define QIXIS_RCW_SRC_NAND 0x110 289 #define QIXIS_RCW_SRC_SD 0x040 290 #define QIXIS_RCW_SRC_QSPI 0x045 291 #define QIXIS_RST_CTL_RESET 0x41 292 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 293 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 294 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 295 296 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 297 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 298 CSPR_PORT_SIZE_8 | \ 299 CSPR_MSEL_GPCM | \ 300 CSPR_V) 301 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 302 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 303 CSOR_NOR_NOR_MODE_AVD_NOR | \ 304 CSOR_NOR_TRHZ_80) 305 306 /* 307 * QIXIS Timing parameters for IFC GPCM 308 */ 309 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 310 FTIM0_GPCM_TEADC(0x20) | \ 311 FTIM0_GPCM_TEAHC(0x10)) 312 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 313 FTIM1_GPCM_TRAD(0x1f)) 314 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 315 FTIM2_GPCM_TCH(0x8) | \ 316 FTIM2_GPCM_TWP(0xf0)) 317 #define CONFIG_SYS_FPGA_FTIM3 0x0 318 #endif 319 320 #ifdef CONFIG_NAND_BOOT 321 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 322 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 323 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 324 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 325 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 326 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 327 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 328 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 329 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 330 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 331 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 332 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 333 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 334 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 335 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 336 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 337 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 338 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 339 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 346 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 347 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 348 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 349 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 350 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 351 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 352 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 353 #else 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 362 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 371 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 372 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 373 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 374 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 375 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 376 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 377 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 378 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 379 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 380 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 381 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 382 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 383 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 384 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 385 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 386 #endif 387 388 /* 389 * I2C bus multiplexer 390 */ 391 #define I2C_MUX_PCA_ADDR_PRI 0x77 392 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 393 #define I2C_RETIMER_ADDR 0x18 394 #define I2C_MUX_CH_DEFAULT 0x8 395 #define I2C_MUX_CH_CH7301 0xC 396 #define I2C_MUX_CH5 0xD 397 #define I2C_MUX_CH6 0xE 398 #define I2C_MUX_CH7 0xF 399 400 #define I2C_MUX_CH_VOL_MONITOR 0xa 401 402 /* Voltage monitor on channel 2*/ 403 #define I2C_VOL_MONITOR_ADDR 0x40 404 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 405 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 406 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 407 408 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 409 #ifndef CONFIG_SPL_BUILD 410 #define CONFIG_VID 411 #endif 412 #define CONFIG_VOL_MONITOR_IR36021_SET 413 #define CONFIG_VOL_MONITOR_INA220 414 /* The lowest and highest voltage allowed for LS1046AQDS */ 415 #define VDD_MV_MIN 819 416 #define VDD_MV_MAX 1212 417 418 /* 419 * Miscellaneous configurable options 420 */ 421 #define CONFIG_MISC_INIT_R 422 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 423 #define CONFIG_AUTO_COMPLETE 424 #define CONFIG_SYS_PBSIZE \ 425 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 426 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 427 428 #define CONFIG_SYS_MEMTEST_START 0x80000000 429 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 430 431 #define CONFIG_SYS_HZ 1000 432 433 #define CONFIG_SYS_INIT_SP_OFFSET \ 434 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 435 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 437 438 /* 439 * Environment 440 */ 441 #define CONFIG_ENV_OVERWRITE 442 443 #ifdef CONFIG_NAND_BOOT 444 #define CONFIG_ENV_SIZE 0x2000 445 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 446 #elif defined(CONFIG_SD_BOOT) 447 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 448 #define CONFIG_SYS_MMC_ENV_DEV 0 449 #define CONFIG_ENV_SIZE 0x2000 450 #elif defined(CONFIG_QSPI_BOOT) 451 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 452 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 453 #define CONFIG_ENV_SECT_SIZE 0x10000 454 #else 455 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 456 #define CONFIG_ENV_SECT_SIZE 0x20000 457 #define CONFIG_ENV_SIZE 0x20000 458 #endif 459 460 #define CONFIG_CMDLINE_TAG 461 462 #undef CONFIG_BOOTCOMMAND 463 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 464 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 465 "e0000 f00000 && bootm $kernel_load" 466 #else 467 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 468 "$kernel_size && bootm $kernel_load" 469 #endif 470 471 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 472 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ 473 "14m(free)" 474 #else 475 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ 476 "2m@0x100000(nor_bank0_uboot),"\ 477 "40m@0x1100000(nor_bank0_fit)," \ 478 "7m(nor_bank0_user)," \ 479 "2m@0x4100000(nor_bank4_uboot)," \ 480 "40m@0x5100000(nor_bank4_fit),"\ 481 "-(nor_bank4_user);" \ 482 "7e800000.flash:" \ 483 "4m(nand_uboot),36m(nand_kernel)," \ 484 "472m(nand_free);spi0.0:2m(uboot)," \ 485 "14m(free)" 486 #endif 487 488 #include <asm/fsl_secure_boot.h> 489 490 #endif /* __LS1046AQDS_H__ */ 491