1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1046AQDS_H__ 7 #define __LS1046AQDS_H__ 8 9 #include "ls1046a_common.h" 10 11 #ifndef __ASSEMBLY__ 12 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_ddr_clk(void); 14 #endif 15 16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 24 /* Physical Memory Map */ 25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 27 #define CONFIG_DDR_SPD 28 #define SPD_EEPROM_ADDRESS 0x51 29 #define CONFIG_SYS_SPD_BUS_NUM 0 30 31 #ifndef CONFIG_SPL 32 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 33 #endif 34 35 #define CONFIG_DDR_ECC 36 #ifdef CONFIG_DDR_ECC 37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #endif 40 41 /* DSPI */ 42 #ifdef CONFIG_FSL_DSPI 43 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 44 #define CONFIG_SPI_FLASH_SST /* cs1 */ 45 #define CONFIG_SPI_FLASH_EON /* cs2 */ 46 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 47 #define CONFIG_SF_DEFAULT_BUS 1 48 #define CONFIG_SF_DEFAULT_CS 0 49 #endif 50 #endif 51 52 /* QSPI */ 53 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 54 #ifdef CONFIG_FSL_QSPI 55 #define CONFIG_SPI_FLASH_SPANSION 56 #define FSL_QSPI_FLASH_SIZE (1 << 24) 57 #define FSL_QSPI_FLASH_NUM 2 58 #endif 59 #endif 60 61 #ifdef CONFIG_SYS_DPAA_FMAN 62 #define CONFIG_FMAN_ENET 63 #define CONFIG_PHY_VITESSE 64 #define CONFIG_PHY_REALTEK 65 #define CONFIG_PHYLIB_10G 66 #define RGMII_PHY1_ADDR 0x1 67 #define RGMII_PHY2_ADDR 0x2 68 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 69 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 70 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 71 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 72 /* PHY address on QSGMII riser card on slot 2 */ 73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 77 #endif 78 79 #ifdef CONFIG_RAMBOOT_PBL 80 #define CONFIG_SYS_FSL_PBL_PBI \ 81 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 82 #endif 83 84 #ifdef CONFIG_NAND_BOOT 85 #define CONFIG_SYS_FSL_PBL_RCW \ 86 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 87 #endif 88 89 #ifdef CONFIG_SD_BOOT 90 #ifdef CONFIG_SD_BOOT_QSPI 91 #define CONFIG_SYS_FSL_PBL_RCW \ 92 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 93 #else 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 96 #endif 97 #endif 98 99 /* IFC */ 100 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 101 #define CONFIG_FSL_IFC 102 /* 103 * CONFIG_SYS_FLASH_BASE has the final address (core view) 104 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 105 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 106 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 107 */ 108 #define CONFIG_SYS_FLASH_BASE 0x60000000 109 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 110 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 111 112 #ifdef CONFIG_MTD_NOR_FLASH 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_FLASH_CFI 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 116 #define CONFIG_SYS_FLASH_QUIET_TEST 117 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 118 #endif 119 #endif 120 121 /* LPUART */ 122 #ifdef CONFIG_LPUART 123 #define CONFIG_LPUART_32B_REG 124 #define CFG_UART_MUX_MASK 0x6 125 #define CFG_UART_MUX_SHIFT 1 126 #define CFG_LPUART_EN 0x2 127 #endif 128 129 /* EEPROM */ 130 #define CONFIG_ID_EEPROM 131 #define CONFIG_SYS_I2C_EEPROM_NXID 132 #define CONFIG_SYS_EEPROM_BUS_NUM 0 133 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 134 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 137 138 /* 139 * IFC Definitions 140 */ 141 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 142 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 143 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 144 CSPR_PORT_SIZE_16 | \ 145 CSPR_MSEL_NOR | \ 146 CSPR_V) 147 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 148 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 149 + 0x8000000) | \ 150 CSPR_PORT_SIZE_16 | \ 151 CSPR_MSEL_NOR | \ 152 CSPR_V) 153 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 154 155 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 156 CSOR_NOR_TRHZ_80) 157 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 158 FTIM0_NOR_TEADC(0x5) | \ 159 FTIM0_NOR_TAVDS(0x6) | \ 160 FTIM0_NOR_TEAHC(0x5)) 161 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 162 FTIM1_NOR_TRAD_NOR(0x1a) | \ 163 FTIM1_NOR_TSEQRAD_NOR(0x13)) 164 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 165 FTIM2_NOR_TCH(0x8) | \ 166 FTIM2_NOR_TWPH(0xe) | \ 167 FTIM2_NOR_TWP(0x1c)) 168 #define CONFIG_SYS_NOR_FTIM3 0 169 170 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 177 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 178 179 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 180 #define CONFIG_SYS_WRITE_SWAPPED_DATA 181 182 /* 183 * NAND Flash Definitions 184 */ 185 #define CONFIG_NAND_FSL_IFC 186 187 #define CONFIG_SYS_NAND_BASE 0x7e800000 188 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 189 190 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 191 192 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 193 | CSPR_PORT_SIZE_8 \ 194 | CSPR_MSEL_NAND \ 195 | CSPR_V) 196 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 197 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 198 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 199 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 200 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 201 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 202 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 203 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 204 205 #define CONFIG_SYS_NAND_ONFI_DETECTION 206 207 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 208 FTIM0_NAND_TWP(0x18) | \ 209 FTIM0_NAND_TWCHT(0x7) | \ 210 FTIM0_NAND_TWH(0xa)) 211 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 212 FTIM1_NAND_TWBE(0x39) | \ 213 FTIM1_NAND_TRR(0xe) | \ 214 FTIM1_NAND_TRP(0x18)) 215 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 216 FTIM2_NAND_TREH(0xa) | \ 217 FTIM2_NAND_TWHRE(0x1e)) 218 #define CONFIG_SYS_NAND_FTIM3 0x0 219 220 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 221 #define CONFIG_SYS_MAX_NAND_DEVICE 1 222 #define CONFIG_MTD_NAND_VERIFY_WRITE 223 224 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 225 #endif 226 227 #ifdef CONFIG_NAND_BOOT 228 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 230 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 231 #endif 232 233 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 234 #define CONFIG_QIXIS_I2C_ACCESS 235 #define CONFIG_SYS_I2C_EARLY_INIT 236 #endif 237 238 /* 239 * QIXIS Definitions 240 */ 241 #define CONFIG_FSL_QIXIS 242 243 #ifdef CONFIG_FSL_QIXIS 244 #define QIXIS_BASE 0x7fb00000 245 #define QIXIS_BASE_PHYS QIXIS_BASE 246 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 247 #define QIXIS_LBMAP_SWITCH 6 248 #define QIXIS_LBMAP_MASK 0x0f 249 #define QIXIS_LBMAP_SHIFT 0 250 #define QIXIS_LBMAP_DFLTBANK 0x00 251 #define QIXIS_LBMAP_ALTBANK 0x04 252 #define QIXIS_LBMAP_NAND 0x09 253 #define QIXIS_LBMAP_SD 0x00 254 #define QIXIS_LBMAP_SD_QSPI 0xff 255 #define QIXIS_LBMAP_QSPI 0xff 256 #define QIXIS_RCW_SRC_NAND 0x110 257 #define QIXIS_RCW_SRC_SD 0x040 258 #define QIXIS_RCW_SRC_QSPI 0x045 259 #define QIXIS_RST_CTL_RESET 0x41 260 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 261 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 262 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 263 264 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 265 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 266 CSPR_PORT_SIZE_8 | \ 267 CSPR_MSEL_GPCM | \ 268 CSPR_V) 269 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 270 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 271 CSOR_NOR_NOR_MODE_AVD_NOR | \ 272 CSOR_NOR_TRHZ_80) 273 274 /* 275 * QIXIS Timing parameters for IFC GPCM 276 */ 277 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 278 FTIM0_GPCM_TEADC(0x20) | \ 279 FTIM0_GPCM_TEAHC(0x10)) 280 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 281 FTIM1_GPCM_TRAD(0x1f)) 282 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 283 FTIM2_GPCM_TCH(0x8) | \ 284 FTIM2_GPCM_TWP(0xf0)) 285 #define CONFIG_SYS_FPGA_FTIM3 0x0 286 #endif 287 288 #ifdef CONFIG_NAND_BOOT 289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 314 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 315 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 316 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 317 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 318 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 319 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 320 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 321 #else 322 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 331 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 332 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 339 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 340 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 341 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 342 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 343 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 344 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 345 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 346 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 347 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 348 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 349 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 350 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 351 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 352 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 353 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 354 #endif 355 356 /* 357 * I2C bus multiplexer 358 */ 359 #define I2C_MUX_PCA_ADDR_PRI 0x77 360 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 361 #define I2C_RETIMER_ADDR 0x18 362 #define I2C_MUX_CH_DEFAULT 0x8 363 #define I2C_MUX_CH_CH7301 0xC 364 #define I2C_MUX_CH5 0xD 365 #define I2C_MUX_CH6 0xE 366 #define I2C_MUX_CH7 0xF 367 368 #define I2C_MUX_CH_VOL_MONITOR 0xa 369 370 /* Voltage monitor on channel 2*/ 371 #define I2C_VOL_MONITOR_ADDR 0x40 372 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 373 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 374 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 375 376 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 377 #ifndef CONFIG_SPL_BUILD 378 #define CONFIG_VID 379 #endif 380 #define CONFIG_VOL_MONITOR_IR36021_SET 381 #define CONFIG_VOL_MONITOR_INA220 382 /* The lowest and highest voltage allowed for LS1046AQDS */ 383 #define VDD_MV_MIN 819 384 #define VDD_MV_MAX 1212 385 386 /* 387 * Miscellaneous configurable options 388 */ 389 390 #define CONFIG_SYS_MEMTEST_START 0x80000000 391 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 392 393 #define CONFIG_SYS_HZ 1000 394 395 #define CONFIG_SYS_INIT_SP_OFFSET \ 396 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 397 398 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 399 400 /* 401 * Environment 402 */ 403 #define CONFIG_ENV_OVERWRITE 404 405 #ifdef CONFIG_NAND_BOOT 406 #define CONFIG_ENV_SIZE 0x2000 407 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 408 #elif defined(CONFIG_SD_BOOT) 409 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 410 #define CONFIG_SYS_MMC_ENV_DEV 0 411 #define CONFIG_ENV_SIZE 0x2000 412 #elif defined(CONFIG_QSPI_BOOT) 413 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 414 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 415 #define CONFIG_ENV_SECT_SIZE 0x10000 416 #else 417 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 418 #define CONFIG_ENV_SECT_SIZE 0x20000 419 #define CONFIG_ENV_SIZE 0x20000 420 #endif 421 422 #define CONFIG_CMDLINE_TAG 423 424 #undef CONFIG_BOOTCOMMAND 425 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 426 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 427 "e0000 f00000 && bootm $kernel_load" 428 #else 429 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 430 "$kernel_size && bootm $kernel_load" 431 #endif 432 433 #include <asm/fsl_secure_boot.h> 434 435 #endif /* __LS1046AQDS_H__ */ 436