1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40010000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 42 43 #define CONFIG_DDR_ECC 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 /* DSPI */ 50 #ifdef CONFIG_FSL_DSPI 51 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 52 #define CONFIG_SPI_FLASH_SST /* cs1 */ 53 #define CONFIG_SPI_FLASH_EON /* cs2 */ 54 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 55 #define CONFIG_SF_DEFAULT_BUS 1 56 #define CONFIG_SF_DEFAULT_CS 0 57 #endif 58 #endif 59 60 /* QSPI */ 61 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 62 #ifdef CONFIG_FSL_QSPI 63 #define CONFIG_SPI_FLASH_SPANSION 64 #define FSL_QSPI_FLASH_SIZE (1 << 24) 65 #define FSL_QSPI_FLASH_NUM 2 66 #endif 67 #endif 68 69 #ifdef CONFIG_SYS_DPAA_FMAN 70 #define CONFIG_FMAN_ENET 71 #define CONFIG_PHYLIB 72 #define CONFIG_PHY_VITESSE 73 #define CONFIG_PHY_REALTEK 74 #define CONFIG_PHYLIB_10G 75 #define RGMII_PHY1_ADDR 0x1 76 #define RGMII_PHY2_ADDR 0x2 77 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 78 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 79 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 80 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 81 /* PHY address on QSGMII riser card on slot 2 */ 82 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 83 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 84 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 85 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 86 #endif 87 88 #ifdef CONFIG_RAMBOOT_PBL 89 #define CONFIG_SYS_FSL_PBL_PBI \ 90 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 91 #endif 92 93 #ifdef CONFIG_NAND_BOOT 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 96 #endif 97 98 #ifdef CONFIG_SD_BOOT 99 #ifdef CONFIG_SD_BOOT_QSPI 100 #define CONFIG_SYS_FSL_PBL_RCW \ 101 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 102 #else 103 #define CONFIG_SYS_FSL_PBL_RCW \ 104 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 105 #endif 106 #endif 107 108 /* IFC */ 109 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 110 #define CONFIG_FSL_IFC 111 /* 112 * CONFIG_SYS_FLASH_BASE has the final address (core view) 113 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 114 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 115 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 116 */ 117 #define CONFIG_SYS_FLASH_BASE 0x60000000 118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 119 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 120 121 #ifndef CONFIG_SYS_NO_FLASH 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 125 #define CONFIG_SYS_FLASH_QUIET_TEST 126 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 127 #endif 128 #endif 129 130 /* LPUART */ 131 #ifdef CONFIG_LPUART 132 #define CONFIG_LPUART_32B_REG 133 #define CFG_UART_MUX_MASK 0x6 134 #define CFG_UART_MUX_SHIFT 1 135 #define CFG_LPUART_EN 0x2 136 #endif 137 138 /* SATA */ 139 #define CONFIG_LIBATA 140 #define CONFIG_SCSI_AHCI 141 #define CONFIG_SCSI_AHCI_PLAT 142 #define CONFIG_SCSI 143 #define CONFIG_DOS_PARTITION 144 #define CONFIG_BOARD_LATE_INIT 145 146 #define CONFIG_PARTITION_UUIDS 147 #define CONFIG_EFI_PARTITION 148 #define CONFIG_CMD_GPT 149 150 /* EEPROM */ 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 159 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 160 161 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 162 #define CONFIG_SYS_SCSI_MAX_LUN 1 163 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 164 CONFIG_SYS_SCSI_MAX_LUN) 165 166 /* 167 * IFC Definitions 168 */ 169 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 170 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 176 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 177 + 0x8000000) | \ 178 CSPR_PORT_SIZE_16 | \ 179 CSPR_MSEL_NOR | \ 180 CSPR_V) 181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 182 183 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 184 CSOR_NOR_TRHZ_80) 185 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 186 FTIM0_NOR_TEADC(0x5) | \ 187 FTIM0_NOR_TEAHC(0x5)) 188 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 189 FTIM1_NOR_TRAD_NOR(0x1a) | \ 190 FTIM1_NOR_TSEQRAD_NOR(0x13)) 191 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 192 FTIM2_NOR_TCH(0x4) | \ 193 FTIM2_NOR_TWPH(0xe) | \ 194 FTIM2_NOR_TWP(0x1c)) 195 #define CONFIG_SYS_NOR_FTIM3 0 196 197 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 198 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 201 202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 204 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 205 206 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 207 #define CONFIG_SYS_WRITE_SWAPPED_DATA 208 209 /* 210 * NAND Flash Definitions 211 */ 212 #define CONFIG_NAND_FSL_IFC 213 214 #define CONFIG_SYS_NAND_BASE 0x7e800000 215 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 216 217 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 218 219 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 220 | CSPR_PORT_SIZE_8 \ 221 | CSPR_MSEL_NAND \ 222 | CSPR_V) 223 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 224 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 225 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 226 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 227 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 228 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 229 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 230 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 231 232 #define CONFIG_SYS_NAND_ONFI_DETECTION 233 234 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 235 FTIM0_NAND_TWP(0x18) | \ 236 FTIM0_NAND_TWCHT(0x7) | \ 237 FTIM0_NAND_TWH(0xa)) 238 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 239 FTIM1_NAND_TWBE(0x39) | \ 240 FTIM1_NAND_TRR(0xe) | \ 241 FTIM1_NAND_TRP(0x18)) 242 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 243 FTIM2_NAND_TREH(0xa) | \ 244 FTIM2_NAND_TWHRE(0x1e)) 245 #define CONFIG_SYS_NAND_FTIM3 0x0 246 247 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_MTD_NAND_VERIFY_WRITE 250 #define CONFIG_CMD_NAND 251 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 253 #endif 254 255 #ifdef CONFIG_NAND_BOOT 256 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 257 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 258 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 259 #endif 260 261 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 262 #define CONFIG_QIXIS_I2C_ACCESS 263 #define CONFIG_SYS_I2C_EARLY_INIT 264 #define CONFIG_SYS_NO_FLASH 265 #endif 266 267 /* 268 * QIXIS Definitions 269 */ 270 #define CONFIG_FSL_QIXIS 271 272 #ifdef CONFIG_FSL_QIXIS 273 #define QIXIS_BASE 0x7fb00000 274 #define QIXIS_BASE_PHYS QIXIS_BASE 275 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 276 #define QIXIS_LBMAP_SWITCH 6 277 #define QIXIS_LBMAP_MASK 0x0f 278 #define QIXIS_LBMAP_SHIFT 0 279 #define QIXIS_LBMAP_DFLTBANK 0x00 280 #define QIXIS_LBMAP_ALTBANK 0x04 281 #define QIXIS_LBMAP_NAND 0x09 282 #define QIXIS_LBMAP_SD 0x00 283 #define QIXIS_LBMAP_SD_QSPI 0xff 284 #define QIXIS_LBMAP_QSPI 0xff 285 #define QIXIS_RCW_SRC_NAND 0x110 286 #define QIXIS_RCW_SRC_SD 0x040 287 #define QIXIS_RCW_SRC_QSPI 0x045 288 #define QIXIS_RST_CTL_RESET 0x41 289 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 290 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 291 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 292 293 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 294 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 295 CSPR_PORT_SIZE_8 | \ 296 CSPR_MSEL_GPCM | \ 297 CSPR_V) 298 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 299 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 300 CSOR_NOR_NOR_MODE_AVD_NOR | \ 301 CSOR_NOR_TRHZ_80) 302 303 /* 304 * QIXIS Timing parameters for IFC GPCM 305 */ 306 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 307 FTIM0_GPCM_TEADC(0x20) | \ 308 FTIM0_GPCM_TEAHC(0x10)) 309 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 310 FTIM1_GPCM_TRAD(0x1f)) 311 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 312 FTIM2_GPCM_TCH(0x8) | \ 313 FTIM2_GPCM_TWP(0xf0)) 314 #define CONFIG_SYS_FPGA_FTIM3 0x0 315 #endif 316 317 #ifdef CONFIG_NAND_BOOT 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 343 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 344 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 345 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 346 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 347 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 348 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 349 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 350 #else 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 375 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 376 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 377 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 378 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 379 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 380 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 381 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 382 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 383 #endif 384 385 /* 386 * I2C bus multiplexer 387 */ 388 #define I2C_MUX_PCA_ADDR_PRI 0x77 389 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 390 #define I2C_RETIMER_ADDR 0x18 391 #define I2C_MUX_CH_DEFAULT 0x8 392 #define I2C_MUX_CH_CH7301 0xC 393 #define I2C_MUX_CH5 0xD 394 #define I2C_MUX_CH6 0xE 395 #define I2C_MUX_CH7 0xF 396 397 #define I2C_MUX_CH_VOL_MONITOR 0xa 398 399 /* Voltage monitor on channel 2*/ 400 #define I2C_VOL_MONITOR_ADDR 0x40 401 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 402 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 403 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 404 405 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 406 #ifndef CONFIG_SPL_BUILD 407 #define CONFIG_VID 408 #endif 409 #define CONFIG_VOL_MONITOR_IR36021_SET 410 #define CONFIG_VOL_MONITOR_INA220 411 /* The lowest and highest voltage allowed for LS1046AQDS */ 412 #define VDD_MV_MIN 819 413 #define VDD_MV_MAX 1212 414 415 /* 416 * Miscellaneous configurable options 417 */ 418 #define CONFIG_MISC_INIT_R 419 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 420 #define CONFIG_AUTO_COMPLETE 421 #define CONFIG_SYS_PBSIZE \ 422 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 423 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 424 425 #define CONFIG_SYS_MEMTEST_START 0x80000000 426 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 427 428 #define CONFIG_SYS_HZ 1000 429 430 /* 431 * Stack sizes 432 * The stack sizes are set up in start.S using the settings below 433 */ 434 #define CONFIG_STACKSIZE (30 * 1024) 435 436 #define CONFIG_SYS_INIT_SP_OFFSET \ 437 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 438 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 440 441 /* 442 * Environment 443 */ 444 #define CONFIG_ENV_OVERWRITE 445 446 #ifdef CONFIG_NAND_BOOT 447 #define CONFIG_ENV_IS_IN_NAND 448 #define CONFIG_ENV_SIZE 0x2000 449 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 450 #elif defined(CONFIG_SD_BOOT) 451 #define CONFIG_ENV_OFFSET (1024 * 1024) 452 #define CONFIG_ENV_IS_IN_MMC 453 #define CONFIG_SYS_MMC_ENV_DEV 0 454 #define CONFIG_ENV_SIZE 0x2000 455 #elif defined(CONFIG_QSPI_BOOT) 456 #define CONFIG_ENV_IS_IN_SPI_FLASH 457 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 458 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 459 #define CONFIG_ENV_SECT_SIZE 0x10000 460 #else 461 #define CONFIG_ENV_IS_IN_FLASH 462 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 463 #define CONFIG_ENV_SECT_SIZE 0x20000 464 #define CONFIG_ENV_SIZE 0x20000 465 #endif 466 467 #define CONFIG_CMDLINE_TAG 468 469 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 470 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 471 "e0000 f00000 && bootm $kernel_load" 472 #else 473 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 474 "$kernel_size && bootm $kernel_load" 475 #endif 476 477 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 478 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ 479 "14m(free)" 480 #else 481 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 482 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 483 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 484 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 485 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 486 "40m(nor_bank4_fit);7e800000.flash:" \ 487 "4m(nand_uboot),36m(nand_kernel)," \ 488 "472m(nand_free);spi0.0:2m(uboot)," \ 489 "14m(free)" 490 #endif 491 492 #include <asm/fsl_secure_boot.h> 493 494 #endif /* __LS1046AQDS_H__ */ 495