1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1046AQDS_H__ 7 #define __LS1046AQDS_H__ 8 9 #include "ls1046a_common.h" 10 11 #ifndef __ASSEMBLY__ 12 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_ddr_clk(void); 14 #endif 15 16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 24 /* Physical Memory Map */ 25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 #define CONFIG_NR_DRAM_BANKS 2 27 28 #define CONFIG_DDR_SPD 29 #define SPD_EEPROM_ADDRESS 0x51 30 #define CONFIG_SYS_SPD_BUS_NUM 0 31 32 #ifndef CONFIG_SPL 33 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 34 #endif 35 36 #define CONFIG_DDR_ECC 37 #ifdef CONFIG_DDR_ECC 38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 39 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 40 #endif 41 42 /* DSPI */ 43 #ifdef CONFIG_FSL_DSPI 44 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 45 #define CONFIG_SPI_FLASH_SST /* cs1 */ 46 #define CONFIG_SPI_FLASH_EON /* cs2 */ 47 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SF_DEFAULT_BUS 1 49 #define CONFIG_SF_DEFAULT_CS 0 50 #endif 51 #endif 52 53 /* QSPI */ 54 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 55 #ifdef CONFIG_FSL_QSPI 56 #define CONFIG_SPI_FLASH_SPANSION 57 #define FSL_QSPI_FLASH_SIZE (1 << 24) 58 #define FSL_QSPI_FLASH_NUM 2 59 #endif 60 #endif 61 62 #ifdef CONFIG_SYS_DPAA_FMAN 63 #define CONFIG_FMAN_ENET 64 #define CONFIG_PHY_VITESSE 65 #define CONFIG_PHY_REALTEK 66 #define CONFIG_PHYLIB_10G 67 #define RGMII_PHY1_ADDR 0x1 68 #define RGMII_PHY2_ADDR 0x2 69 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 70 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 71 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 72 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 73 /* PHY address on QSGMII riser card on slot 2 */ 74 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 75 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 76 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 77 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 78 #endif 79 80 #ifdef CONFIG_RAMBOOT_PBL 81 #define CONFIG_SYS_FSL_PBL_PBI \ 82 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 83 #endif 84 85 #ifdef CONFIG_NAND_BOOT 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 88 #endif 89 90 #ifdef CONFIG_SD_BOOT 91 #ifdef CONFIG_SD_BOOT_QSPI 92 #define CONFIG_SYS_FSL_PBL_RCW \ 93 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 94 #else 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 97 #endif 98 #endif 99 100 /* IFC */ 101 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 102 #define CONFIG_FSL_IFC 103 /* 104 * CONFIG_SYS_FLASH_BASE has the final address (core view) 105 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 106 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 107 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 108 */ 109 #define CONFIG_SYS_FLASH_BASE 0x60000000 110 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 111 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 112 113 #ifdef CONFIG_MTD_NOR_FLASH 114 #define CONFIG_FLASH_CFI_DRIVER 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 117 #define CONFIG_SYS_FLASH_QUIET_TEST 118 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 119 #endif 120 #endif 121 122 /* LPUART */ 123 #ifdef CONFIG_LPUART 124 #define CONFIG_LPUART_32B_REG 125 #define CFG_UART_MUX_MASK 0x6 126 #define CFG_UART_MUX_SHIFT 1 127 #define CFG_LPUART_EN 0x2 128 #endif 129 130 /* EEPROM */ 131 #define CONFIG_ID_EEPROM 132 #define CONFIG_SYS_I2C_EEPROM_NXID 133 #define CONFIG_SYS_EEPROM_BUS_NUM 0 134 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 137 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 138 139 /* 140 * IFC Definitions 141 */ 142 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 143 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 144 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 145 CSPR_PORT_SIZE_16 | \ 146 CSPR_MSEL_NOR | \ 147 CSPR_V) 148 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 149 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 150 + 0x8000000) | \ 151 CSPR_PORT_SIZE_16 | \ 152 CSPR_MSEL_NOR | \ 153 CSPR_V) 154 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 155 156 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 157 CSOR_NOR_TRHZ_80) 158 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 159 FTIM0_NOR_TEADC(0x5) | \ 160 FTIM0_NOR_TAVDS(0x6) | \ 161 FTIM0_NOR_TEAHC(0x5)) 162 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 163 FTIM1_NOR_TRAD_NOR(0x1a) | \ 164 FTIM1_NOR_TSEQRAD_NOR(0x13)) 165 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 166 FTIM2_NOR_TCH(0x8) | \ 167 FTIM2_NOR_TWPH(0xe) | \ 168 FTIM2_NOR_TWP(0x1c)) 169 #define CONFIG_SYS_NOR_FTIM3 0 170 171 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 172 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 175 176 #define CONFIG_SYS_FLASH_EMPTY_INFO 177 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 178 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 179 180 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 181 #define CONFIG_SYS_WRITE_SWAPPED_DATA 182 183 /* 184 * NAND Flash Definitions 185 */ 186 #define CONFIG_NAND_FSL_IFC 187 188 #define CONFIG_SYS_NAND_BASE 0x7e800000 189 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 190 191 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 192 193 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 194 | CSPR_PORT_SIZE_8 \ 195 | CSPR_MSEL_NAND \ 196 | CSPR_V) 197 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 198 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 199 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 200 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 201 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 202 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 203 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 204 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 205 206 #define CONFIG_SYS_NAND_ONFI_DETECTION 207 208 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 209 FTIM0_NAND_TWP(0x18) | \ 210 FTIM0_NAND_TWCHT(0x7) | \ 211 FTIM0_NAND_TWH(0xa)) 212 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 213 FTIM1_NAND_TWBE(0x39) | \ 214 FTIM1_NAND_TRR(0xe) | \ 215 FTIM1_NAND_TRP(0x18)) 216 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 217 FTIM2_NAND_TREH(0xa) | \ 218 FTIM2_NAND_TWHRE(0x1e)) 219 #define CONFIG_SYS_NAND_FTIM3 0x0 220 221 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 222 #define CONFIG_SYS_MAX_NAND_DEVICE 1 223 #define CONFIG_MTD_NAND_VERIFY_WRITE 224 225 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 226 #endif 227 228 #ifdef CONFIG_NAND_BOOT 229 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 230 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 231 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 232 #endif 233 234 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 235 #define CONFIG_QIXIS_I2C_ACCESS 236 #define CONFIG_SYS_I2C_EARLY_INIT 237 #endif 238 239 /* 240 * QIXIS Definitions 241 */ 242 #define CONFIG_FSL_QIXIS 243 244 #ifdef CONFIG_FSL_QIXIS 245 #define QIXIS_BASE 0x7fb00000 246 #define QIXIS_BASE_PHYS QIXIS_BASE 247 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 248 #define QIXIS_LBMAP_SWITCH 6 249 #define QIXIS_LBMAP_MASK 0x0f 250 #define QIXIS_LBMAP_SHIFT 0 251 #define QIXIS_LBMAP_DFLTBANK 0x00 252 #define QIXIS_LBMAP_ALTBANK 0x04 253 #define QIXIS_LBMAP_NAND 0x09 254 #define QIXIS_LBMAP_SD 0x00 255 #define QIXIS_LBMAP_SD_QSPI 0xff 256 #define QIXIS_LBMAP_QSPI 0xff 257 #define QIXIS_RCW_SRC_NAND 0x110 258 #define QIXIS_RCW_SRC_SD 0x040 259 #define QIXIS_RCW_SRC_QSPI 0x045 260 #define QIXIS_RST_CTL_RESET 0x41 261 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 262 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 263 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 264 265 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 266 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 267 CSPR_PORT_SIZE_8 | \ 268 CSPR_MSEL_GPCM | \ 269 CSPR_V) 270 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 271 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 272 CSOR_NOR_NOR_MODE_AVD_NOR | \ 273 CSOR_NOR_TRHZ_80) 274 275 /* 276 * QIXIS Timing parameters for IFC GPCM 277 */ 278 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 279 FTIM0_GPCM_TEADC(0x20) | \ 280 FTIM0_GPCM_TEAHC(0x10)) 281 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 282 FTIM1_GPCM_TRAD(0x1f)) 283 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 284 FTIM2_GPCM_TCH(0x8) | \ 285 FTIM2_GPCM_TWP(0xf0)) 286 #define CONFIG_SYS_FPGA_FTIM3 0x0 287 #endif 288 289 #ifdef CONFIG_NAND_BOOT 290 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 291 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 292 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 293 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 294 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 295 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 296 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 297 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 298 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 299 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 300 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 307 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 308 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 315 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 316 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 317 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 318 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 319 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 320 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 321 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 322 #else 323 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 332 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 333 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 340 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 341 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 342 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 343 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 344 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 345 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 346 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 347 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 348 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 349 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 350 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 351 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 352 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 353 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 354 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 355 #endif 356 357 /* 358 * I2C bus multiplexer 359 */ 360 #define I2C_MUX_PCA_ADDR_PRI 0x77 361 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 362 #define I2C_RETIMER_ADDR 0x18 363 #define I2C_MUX_CH_DEFAULT 0x8 364 #define I2C_MUX_CH_CH7301 0xC 365 #define I2C_MUX_CH5 0xD 366 #define I2C_MUX_CH6 0xE 367 #define I2C_MUX_CH7 0xF 368 369 #define I2C_MUX_CH_VOL_MONITOR 0xa 370 371 /* Voltage monitor on channel 2*/ 372 #define I2C_VOL_MONITOR_ADDR 0x40 373 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 374 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 375 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 376 377 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 378 #ifndef CONFIG_SPL_BUILD 379 #define CONFIG_VID 380 #endif 381 #define CONFIG_VOL_MONITOR_IR36021_SET 382 #define CONFIG_VOL_MONITOR_INA220 383 /* The lowest and highest voltage allowed for LS1046AQDS */ 384 #define VDD_MV_MIN 819 385 #define VDD_MV_MAX 1212 386 387 /* 388 * Miscellaneous configurable options 389 */ 390 #define CONFIG_MISC_INIT_R 391 392 #define CONFIG_SYS_MEMTEST_START 0x80000000 393 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 394 395 #define CONFIG_SYS_HZ 1000 396 397 #define CONFIG_SYS_INIT_SP_OFFSET \ 398 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 399 400 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 401 402 /* 403 * Environment 404 */ 405 #define CONFIG_ENV_OVERWRITE 406 407 #ifdef CONFIG_NAND_BOOT 408 #define CONFIG_ENV_SIZE 0x2000 409 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 410 #elif defined(CONFIG_SD_BOOT) 411 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 412 #define CONFIG_SYS_MMC_ENV_DEV 0 413 #define CONFIG_ENV_SIZE 0x2000 414 #elif defined(CONFIG_QSPI_BOOT) 415 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 416 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 417 #define CONFIG_ENV_SECT_SIZE 0x10000 418 #else 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 420 #define CONFIG_ENV_SECT_SIZE 0x20000 421 #define CONFIG_ENV_SIZE 0x20000 422 #endif 423 424 #define CONFIG_CMDLINE_TAG 425 426 #undef CONFIG_BOOTCOMMAND 427 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 428 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 429 "e0000 f00000 && bootm $kernel_load" 430 #else 431 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 432 "$kernel_size && bootm $kernel_load" 433 #endif 434 435 #include <asm/fsl_secure_boot.h> 436 437 #endif /* __LS1046AQDS_H__ */ 438