1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40010000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 42 43 #define CONFIG_DDR_ECC 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 /* DSPI */ 50 #ifdef CONFIG_FSL_DSPI 51 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 52 #define CONFIG_SPI_FLASH_SST /* cs1 */ 53 #define CONFIG_SPI_FLASH_EON /* cs2 */ 54 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 55 #define CONFIG_SF_DEFAULT_BUS 1 56 #define CONFIG_SF_DEFAULT_CS 0 57 #endif 58 #endif 59 60 /* QSPI */ 61 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 62 #ifdef CONFIG_FSL_QSPI 63 #define CONFIG_SPI_FLASH_SPANSION 64 #define FSL_QSPI_FLASH_SIZE (1 << 24) 65 #define FSL_QSPI_FLASH_NUM 2 66 #endif 67 #endif 68 69 #ifdef CONFIG_SYS_DPAA_FMAN 70 #define CONFIG_FMAN_ENET 71 #define CONFIG_PHYLIB 72 #define CONFIG_PHY_VITESSE 73 #define CONFIG_PHY_REALTEK 74 #define CONFIG_PHYLIB_10G 75 #define RGMII_PHY1_ADDR 0x1 76 #define RGMII_PHY2_ADDR 0x2 77 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 78 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 79 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 80 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 81 /* PHY address on QSGMII riser card on slot 2 */ 82 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 83 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 84 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 85 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 86 #endif 87 88 #ifdef CONFIG_RAMBOOT_PBL 89 #define CONFIG_SYS_FSL_PBL_PBI \ 90 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 91 #endif 92 93 #ifdef CONFIG_NAND_BOOT 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 96 #endif 97 98 #ifdef CONFIG_SD_BOOT 99 #ifdef CONFIG_SD_BOOT_QSPI 100 #define CONFIG_SYS_FSL_PBL_RCW \ 101 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 102 #else 103 #define CONFIG_SYS_FSL_PBL_RCW \ 104 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 105 #endif 106 #endif 107 108 /* IFC */ 109 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 110 #define CONFIG_FSL_IFC 111 /* 112 * CONFIG_SYS_FLASH_BASE has the final address (core view) 113 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 114 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 115 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 116 */ 117 #define CONFIG_SYS_FLASH_BASE 0x60000000 118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 119 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 120 121 #ifndef CONFIG_SYS_NO_FLASH 122 #define CONFIG_FLASH_CFI_DRIVER 123 #define CONFIG_SYS_FLASH_CFI 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 125 #define CONFIG_SYS_FLASH_QUIET_TEST 126 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 127 #endif 128 #endif 129 130 /* LPUART */ 131 #ifdef CONFIG_LPUART 132 #define CONFIG_LPUART_32B_REG 133 #define CFG_UART_MUX_MASK 0x6 134 #define CFG_UART_MUX_SHIFT 1 135 #define CFG_LPUART_EN 0x2 136 #endif 137 138 /* SATA */ 139 #define CONFIG_LIBATA 140 #define CONFIG_SCSI_AHCI 141 #define CONFIG_SCSI_AHCI_PLAT 142 #define CONFIG_SCSI 143 #define CONFIG_DOS_PARTITION 144 #define CONFIG_BOARD_LATE_INIT 145 146 /* EEPROM */ 147 #define CONFIG_ID_EEPROM 148 #define CONFIG_SYS_I2C_EEPROM_NXID 149 #define CONFIG_SYS_EEPROM_BUS_NUM 0 150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 154 155 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 156 157 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 158 #define CONFIG_SYS_SCSI_MAX_LUN 1 159 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 160 CONFIG_SYS_SCSI_MAX_LUN) 161 162 /* 163 * IFC Definitions 164 */ 165 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 166 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 167 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 172 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 173 + 0x8000000) | \ 174 CSPR_PORT_SIZE_16 | \ 175 CSPR_MSEL_NOR | \ 176 CSPR_V) 177 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 178 179 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 180 CSOR_NOR_TRHZ_80) 181 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 182 FTIM0_NOR_TEADC(0x5) | \ 183 FTIM0_NOR_TEAHC(0x5)) 184 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 185 FTIM1_NOR_TRAD_NOR(0x1a) | \ 186 FTIM1_NOR_TSEQRAD_NOR(0x13)) 187 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 188 FTIM2_NOR_TCH(0x4) | \ 189 FTIM2_NOR_TWPH(0xe) | \ 190 FTIM2_NOR_TWP(0x1c)) 191 #define CONFIG_SYS_NOR_FTIM3 0 192 193 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 198 #define CONFIG_SYS_FLASH_EMPTY_INFO 199 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 200 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 201 202 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 203 #define CONFIG_SYS_WRITE_SWAPPED_DATA 204 205 /* 206 * NAND Flash Definitions 207 */ 208 #define CONFIG_NAND_FSL_IFC 209 210 #define CONFIG_SYS_NAND_BASE 0x7e800000 211 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 212 213 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 214 215 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 216 | CSPR_PORT_SIZE_8 \ 217 | CSPR_MSEL_NAND \ 218 | CSPR_V) 219 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 220 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 221 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 222 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 223 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 224 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 225 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 226 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 227 228 #define CONFIG_SYS_NAND_ONFI_DETECTION 229 230 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 231 FTIM0_NAND_TWP(0x18) | \ 232 FTIM0_NAND_TWCHT(0x7) | \ 233 FTIM0_NAND_TWH(0xa)) 234 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 235 FTIM1_NAND_TWBE(0x39) | \ 236 FTIM1_NAND_TRR(0xe) | \ 237 FTIM1_NAND_TRP(0x18)) 238 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 239 FTIM2_NAND_TREH(0xa) | \ 240 FTIM2_NAND_TWHRE(0x1e)) 241 #define CONFIG_SYS_NAND_FTIM3 0x0 242 243 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 244 #define CONFIG_SYS_MAX_NAND_DEVICE 1 245 #define CONFIG_MTD_NAND_VERIFY_WRITE 246 #define CONFIG_CMD_NAND 247 248 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 249 #endif 250 251 #ifdef CONFIG_NAND_BOOT 252 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 253 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 254 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 255 #endif 256 257 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 258 #define CONFIG_QIXIS_I2C_ACCESS 259 #define CONFIG_SYS_I2C_EARLY_INIT 260 #define CONFIG_SYS_NO_FLASH 261 #endif 262 263 /* 264 * QIXIS Definitions 265 */ 266 #define CONFIG_FSL_QIXIS 267 268 #ifdef CONFIG_FSL_QIXIS 269 #define QIXIS_BASE 0x7fb00000 270 #define QIXIS_BASE_PHYS QIXIS_BASE 271 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 272 #define QIXIS_LBMAP_SWITCH 6 273 #define QIXIS_LBMAP_MASK 0x0f 274 #define QIXIS_LBMAP_SHIFT 0 275 #define QIXIS_LBMAP_DFLTBANK 0x00 276 #define QIXIS_LBMAP_ALTBANK 0x04 277 #define QIXIS_LBMAP_NAND 0x09 278 #define QIXIS_LBMAP_SD 0x00 279 #define QIXIS_LBMAP_SD_QSPI 0xff 280 #define QIXIS_LBMAP_QSPI 0xff 281 #define QIXIS_RCW_SRC_NAND 0x110 282 #define QIXIS_RCW_SRC_SD 0x040 283 #define QIXIS_RCW_SRC_QSPI 0x045 284 #define QIXIS_RST_CTL_RESET 0x41 285 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 286 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 287 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 288 289 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 290 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 291 CSPR_PORT_SIZE_8 | \ 292 CSPR_MSEL_GPCM | \ 293 CSPR_V) 294 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 295 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 296 CSOR_NOR_NOR_MODE_AVD_NOR | \ 297 CSOR_NOR_TRHZ_80) 298 299 /* 300 * QIXIS Timing parameters for IFC GPCM 301 */ 302 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 303 FTIM0_GPCM_TEADC(0x20) | \ 304 FTIM0_GPCM_TEAHC(0x10)) 305 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 306 FTIM1_GPCM_TRAD(0x1f)) 307 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 308 FTIM2_GPCM_TCH(0x8) | \ 309 FTIM2_GPCM_TWP(0xf0)) 310 #define CONFIG_SYS_FPGA_FTIM3 0x0 311 #endif 312 313 #ifdef CONFIG_NAND_BOOT 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 331 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 332 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 339 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 340 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 341 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 342 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 343 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 344 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 345 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 346 #else 347 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 348 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 349 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 350 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 351 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 352 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 353 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 354 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 355 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 371 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 372 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 373 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 374 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 375 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 376 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 377 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 378 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 379 #endif 380 381 /* 382 * I2C bus multiplexer 383 */ 384 #define I2C_MUX_PCA_ADDR_PRI 0x77 385 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 386 #define I2C_RETIMER_ADDR 0x18 387 #define I2C_MUX_CH_DEFAULT 0x8 388 #define I2C_MUX_CH_CH7301 0xC 389 #define I2C_MUX_CH5 0xD 390 #define I2C_MUX_CH6 0xE 391 #define I2C_MUX_CH7 0xF 392 393 #define I2C_MUX_CH_VOL_MONITOR 0xa 394 395 /* Voltage monitor on channel 2*/ 396 #define I2C_VOL_MONITOR_ADDR 0x40 397 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 398 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 399 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 400 401 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 402 #ifndef CONFIG_SPL_BUILD 403 #define CONFIG_VID 404 #endif 405 #define CONFIG_VOL_MONITOR_IR36021_SET 406 #define CONFIG_VOL_MONITOR_INA220 407 /* The lowest and highest voltage allowed for LS1046AQDS */ 408 #define VDD_MV_MIN 819 409 #define VDD_MV_MAX 1212 410 411 /* 412 * Miscellaneous configurable options 413 */ 414 #define CONFIG_MISC_INIT_R 415 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 416 #define CONFIG_AUTO_COMPLETE 417 #define CONFIG_SYS_PBSIZE \ 418 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 419 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 420 421 #define CONFIG_SYS_MEMTEST_START 0x80000000 422 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 423 424 #define CONFIG_SYS_HZ 1000 425 426 /* 427 * Stack sizes 428 * The stack sizes are set up in start.S using the settings below 429 */ 430 #define CONFIG_STACKSIZE (30 * 1024) 431 432 #define CONFIG_SYS_INIT_SP_OFFSET \ 433 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 434 435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 436 437 /* 438 * Environment 439 */ 440 #define CONFIG_ENV_OVERWRITE 441 442 #ifdef CONFIG_NAND_BOOT 443 #define CONFIG_ENV_IS_IN_NAND 444 #define CONFIG_ENV_SIZE 0x2000 445 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 446 #elif defined(CONFIG_SD_BOOT) 447 #define CONFIG_ENV_OFFSET (1024 * 1024) 448 #define CONFIG_ENV_IS_IN_MMC 449 #define CONFIG_SYS_MMC_ENV_DEV 0 450 #define CONFIG_ENV_SIZE 0x2000 451 #elif defined(CONFIG_QSPI_BOOT) 452 #define CONFIG_ENV_IS_IN_SPI_FLASH 453 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 454 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 455 #define CONFIG_ENV_SECT_SIZE 0x10000 456 #else 457 #define CONFIG_ENV_IS_IN_FLASH 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 459 #define CONFIG_ENV_SECT_SIZE 0x20000 460 #define CONFIG_ENV_SIZE 0x20000 461 #endif 462 463 #define CONFIG_CMDLINE_TAG 464 465 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 466 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 467 "e0000 f00000 && bootm $kernel_load" 468 #else 469 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 470 "$kernel_size && bootm $kernel_load" 471 #endif 472 473 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 474 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \ 475 "14m(free)" 476 #else 477 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 478 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 479 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 480 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 481 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 482 "40m(nor_bank4_fit);7e800000.flash:" \ 483 "4m(nand_uboot),36m(nand_kernel)," \ 484 "472m(nand_free);spi0.0:2m(uboot)," \ 485 "14m(free)" 486 #endif 487 488 #include <asm/fsl_secure_boot.h> 489 490 #endif /* __LS1046AQDS_H__ */ 491