1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40100000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #ifndef CONFIG_SPL 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #endif 44 45 #define CONFIG_DDR_ECC 46 #ifdef CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 51 /* DSPI */ 52 #ifdef CONFIG_FSL_DSPI 53 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 54 #define CONFIG_SPI_FLASH_SST /* cs1 */ 55 #define CONFIG_SPI_FLASH_EON /* cs2 */ 56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 57 #define CONFIG_SF_DEFAULT_BUS 1 58 #define CONFIG_SF_DEFAULT_CS 0 59 #endif 60 #endif 61 62 /* QSPI */ 63 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 64 #ifdef CONFIG_FSL_QSPI 65 #define CONFIG_SPI_FLASH_SPANSION 66 #define FSL_QSPI_FLASH_SIZE (1 << 24) 67 #define FSL_QSPI_FLASH_NUM 2 68 #endif 69 #endif 70 71 #ifdef CONFIG_SYS_DPAA_FMAN 72 #define CONFIG_FMAN_ENET 73 #define CONFIG_PHY_VITESSE 74 #define CONFIG_PHY_REALTEK 75 #define CONFIG_PHYLIB_10G 76 #define RGMII_PHY1_ADDR 0x1 77 #define RGMII_PHY2_ADDR 0x2 78 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 79 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 80 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 81 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 82 /* PHY address on QSGMII riser card on slot 2 */ 83 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 84 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 85 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 86 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 87 #endif 88 89 #ifdef CONFIG_RAMBOOT_PBL 90 #define CONFIG_SYS_FSL_PBL_PBI \ 91 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 92 #endif 93 94 #ifdef CONFIG_NAND_BOOT 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 97 #endif 98 99 #ifdef CONFIG_SD_BOOT 100 #ifdef CONFIG_SD_BOOT_QSPI 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 103 #else 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 106 #endif 107 #endif 108 109 /* IFC */ 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 111 #define CONFIG_FSL_IFC 112 /* 113 * CONFIG_SYS_FLASH_BASE has the final address (core view) 114 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 115 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 116 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 117 */ 118 #define CONFIG_SYS_FLASH_BASE 0x60000000 119 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 121 122 #ifdef CONFIG_MTD_NOR_FLASH 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 126 #define CONFIG_SYS_FLASH_QUIET_TEST 127 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 128 #endif 129 #endif 130 131 /* LPUART */ 132 #ifdef CONFIG_LPUART 133 #define CONFIG_LPUART_32B_REG 134 #define CFG_UART_MUX_MASK 0x6 135 #define CFG_UART_MUX_SHIFT 1 136 #define CFG_LPUART_EN 0x2 137 #endif 138 139 /* SATA */ 140 #define CONFIG_LIBATA 141 #define CONFIG_SCSI_AHCI 142 #define CONFIG_SCSI_AHCI_PLAT 143 144 /* EEPROM */ 145 #define CONFIG_ID_EEPROM 146 #define CONFIG_SYS_I2C_EEPROM_NXID 147 #define CONFIG_SYS_EEPROM_BUS_NUM 0 148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 152 153 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 154 155 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 156 #define CONFIG_SYS_SCSI_MAX_LUN 1 157 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 158 CONFIG_SYS_SCSI_MAX_LUN) 159 160 /* 161 * IFC Definitions 162 */ 163 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 164 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 165 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 166 CSPR_PORT_SIZE_16 | \ 167 CSPR_MSEL_NOR | \ 168 CSPR_V) 169 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 170 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 171 + 0x8000000) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 176 177 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 178 CSOR_NOR_TRHZ_80) 179 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 180 FTIM0_NOR_TEADC(0x5) | \ 181 FTIM0_NOR_TEAHC(0x5)) 182 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 183 FTIM1_NOR_TRAD_NOR(0x1a) | \ 184 FTIM1_NOR_TSEQRAD_NOR(0x13)) 185 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 186 FTIM2_NOR_TCH(0x4) | \ 187 FTIM2_NOR_TWPH(0xe) | \ 188 FTIM2_NOR_TWP(0x1c)) 189 #define CONFIG_SYS_NOR_FTIM3 0 190 191 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 192 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 193 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 194 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 195 196 #define CONFIG_SYS_FLASH_EMPTY_INFO 197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 198 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 199 200 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 201 #define CONFIG_SYS_WRITE_SWAPPED_DATA 202 203 /* 204 * NAND Flash Definitions 205 */ 206 #define CONFIG_NAND_FSL_IFC 207 208 #define CONFIG_SYS_NAND_BASE 0x7e800000 209 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 210 211 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 212 213 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 214 | CSPR_PORT_SIZE_8 \ 215 | CSPR_MSEL_NAND \ 216 | CSPR_V) 217 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 218 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 219 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 220 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 221 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 222 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 223 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 224 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 225 226 #define CONFIG_SYS_NAND_ONFI_DETECTION 227 228 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 229 FTIM0_NAND_TWP(0x18) | \ 230 FTIM0_NAND_TWCHT(0x7) | \ 231 FTIM0_NAND_TWH(0xa)) 232 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 233 FTIM1_NAND_TWBE(0x39) | \ 234 FTIM1_NAND_TRR(0xe) | \ 235 FTIM1_NAND_TRP(0x18)) 236 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 237 FTIM2_NAND_TREH(0xa) | \ 238 FTIM2_NAND_TWHRE(0x1e)) 239 #define CONFIG_SYS_NAND_FTIM3 0x0 240 241 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 242 #define CONFIG_SYS_MAX_NAND_DEVICE 1 243 #define CONFIG_MTD_NAND_VERIFY_WRITE 244 245 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 246 #endif 247 248 #ifdef CONFIG_NAND_BOOT 249 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 250 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 251 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 252 #endif 253 254 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 255 #define CONFIG_QIXIS_I2C_ACCESS 256 #define CONFIG_SYS_I2C_EARLY_INIT 257 #endif 258 259 /* 260 * QIXIS Definitions 261 */ 262 #define CONFIG_FSL_QIXIS 263 264 #ifdef CONFIG_FSL_QIXIS 265 #define QIXIS_BASE 0x7fb00000 266 #define QIXIS_BASE_PHYS QIXIS_BASE 267 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 268 #define QIXIS_LBMAP_SWITCH 6 269 #define QIXIS_LBMAP_MASK 0x0f 270 #define QIXIS_LBMAP_SHIFT 0 271 #define QIXIS_LBMAP_DFLTBANK 0x00 272 #define QIXIS_LBMAP_ALTBANK 0x04 273 #define QIXIS_LBMAP_NAND 0x09 274 #define QIXIS_LBMAP_SD 0x00 275 #define QIXIS_LBMAP_SD_QSPI 0xff 276 #define QIXIS_LBMAP_QSPI 0xff 277 #define QIXIS_RCW_SRC_NAND 0x110 278 #define QIXIS_RCW_SRC_SD 0x040 279 #define QIXIS_RCW_SRC_QSPI 0x045 280 #define QIXIS_RST_CTL_RESET 0x41 281 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 282 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 283 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 284 285 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 286 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 287 CSPR_PORT_SIZE_8 | \ 288 CSPR_MSEL_GPCM | \ 289 CSPR_V) 290 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 291 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 292 CSOR_NOR_NOR_MODE_AVD_NOR | \ 293 CSOR_NOR_TRHZ_80) 294 295 /* 296 * QIXIS Timing parameters for IFC GPCM 297 */ 298 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 299 FTIM0_GPCM_TEADC(0x20) | \ 300 FTIM0_GPCM_TEAHC(0x10)) 301 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 302 FTIM1_GPCM_TRAD(0x1f)) 303 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 304 FTIM2_GPCM_TCH(0x8) | \ 305 FTIM2_GPCM_TWP(0xf0)) 306 #define CONFIG_SYS_FPGA_FTIM3 0x0 307 #endif 308 309 #ifdef CONFIG_NAND_BOOT 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 327 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 328 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 335 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 336 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 337 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 338 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 339 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 340 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 341 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 352 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 353 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 360 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 361 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 362 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 363 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 364 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 365 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 366 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 367 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 368 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 369 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 370 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 371 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 372 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 373 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 374 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 375 #endif 376 377 /* 378 * I2C bus multiplexer 379 */ 380 #define I2C_MUX_PCA_ADDR_PRI 0x77 381 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 382 #define I2C_RETIMER_ADDR 0x18 383 #define I2C_MUX_CH_DEFAULT 0x8 384 #define I2C_MUX_CH_CH7301 0xC 385 #define I2C_MUX_CH5 0xD 386 #define I2C_MUX_CH6 0xE 387 #define I2C_MUX_CH7 0xF 388 389 #define I2C_MUX_CH_VOL_MONITOR 0xa 390 391 /* Voltage monitor on channel 2*/ 392 #define I2C_VOL_MONITOR_ADDR 0x40 393 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 394 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 395 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 396 397 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 398 #ifndef CONFIG_SPL_BUILD 399 #define CONFIG_VID 400 #endif 401 #define CONFIG_VOL_MONITOR_IR36021_SET 402 #define CONFIG_VOL_MONITOR_INA220 403 /* The lowest and highest voltage allowed for LS1046AQDS */ 404 #define VDD_MV_MIN 819 405 #define VDD_MV_MAX 1212 406 407 /* 408 * Miscellaneous configurable options 409 */ 410 #define CONFIG_MISC_INIT_R 411 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 412 #define CONFIG_AUTO_COMPLETE 413 414 #define CONFIG_SYS_MEMTEST_START 0x80000000 415 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 416 417 #define CONFIG_SYS_HZ 1000 418 419 #define CONFIG_SYS_INIT_SP_OFFSET \ 420 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 421 422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 423 424 /* 425 * Environment 426 */ 427 #define CONFIG_ENV_OVERWRITE 428 429 #ifdef CONFIG_NAND_BOOT 430 #define CONFIG_ENV_SIZE 0x2000 431 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 432 #elif defined(CONFIG_SD_BOOT) 433 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 434 #define CONFIG_SYS_MMC_ENV_DEV 0 435 #define CONFIG_ENV_SIZE 0x2000 436 #elif defined(CONFIG_QSPI_BOOT) 437 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 438 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 439 #define CONFIG_ENV_SECT_SIZE 0x10000 440 #else 441 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 442 #define CONFIG_ENV_SECT_SIZE 0x20000 443 #define CONFIG_ENV_SIZE 0x20000 444 #endif 445 446 #define CONFIG_CMDLINE_TAG 447 448 #undef CONFIG_BOOTCOMMAND 449 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 450 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 451 "e0000 f00000 && bootm $kernel_load" 452 #else 453 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 454 "$kernel_size && bootm $kernel_load" 455 #endif 456 457 #include <asm/fsl_secure_boot.h> 458 459 #endif /* __LS1046AQDS_H__ */ 460