1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1046AQDS_H__ 7 #define __LS1046AQDS_H__ 8 9 #include "ls1046a_common.h" 10 11 #ifndef __ASSEMBLY__ 12 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_ddr_clk(void); 14 #endif 15 16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 24 /* Physical Memory Map */ 25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 27 #define CONFIG_DDR_SPD 28 #define SPD_EEPROM_ADDRESS 0x51 29 #define CONFIG_SYS_SPD_BUS_NUM 0 30 31 #ifndef CONFIG_SPL 32 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 33 #endif 34 35 #define CONFIG_DDR_ECC 36 #ifdef CONFIG_DDR_ECC 37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #endif 40 41 /* DSPI */ 42 #ifdef CONFIG_FSL_DSPI 43 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 44 #define CONFIG_SPI_FLASH_SST /* cs1 */ 45 #define CONFIG_SPI_FLASH_EON /* cs2 */ 46 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 47 #define CONFIG_SF_DEFAULT_BUS 1 48 #define CONFIG_SF_DEFAULT_CS 0 49 #endif 50 #endif 51 52 /* QSPI */ 53 #if defined(CONFIG_TFABOOT) || \ 54 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 55 #ifdef CONFIG_FSL_QSPI 56 #define CONFIG_SPI_FLASH_SPANSION 57 #define FSL_QSPI_FLASH_SIZE (1 << 24) 58 #define FSL_QSPI_FLASH_NUM 2 59 #endif 60 #endif 61 62 #ifdef CONFIG_SYS_DPAA_FMAN 63 #define CONFIG_FMAN_ENET 64 #define CONFIG_PHY_VITESSE 65 #define CONFIG_PHY_REALTEK 66 #define CONFIG_PHYLIB_10G 67 #define RGMII_PHY1_ADDR 0x1 68 #define RGMII_PHY2_ADDR 0x2 69 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 70 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 71 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 72 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 73 /* PHY address on QSGMII riser card on slot 2 */ 74 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 75 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 76 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 77 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 78 #endif 79 80 #ifdef CONFIG_RAMBOOT_PBL 81 #define CONFIG_SYS_FSL_PBL_PBI \ 82 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 83 #endif 84 85 #ifdef CONFIG_NAND_BOOT 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 88 #endif 89 90 #ifdef CONFIG_SD_BOOT 91 #ifdef CONFIG_SD_BOOT_QSPI 92 #define CONFIG_SYS_FSL_PBL_RCW \ 93 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 94 #else 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 97 #endif 98 #endif 99 100 /* IFC */ 101 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 102 #define CONFIG_FSL_IFC 103 /* 104 * CONFIG_SYS_FLASH_BASE has the final address (core view) 105 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 106 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 107 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 108 */ 109 #define CONFIG_SYS_FLASH_BASE 0x60000000 110 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 111 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 112 113 #ifdef CONFIG_MTD_NOR_FLASH 114 #define CONFIG_SYS_FLASH_QUIET_TEST 115 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 116 #endif 117 #endif 118 119 /* LPUART */ 120 #ifdef CONFIG_LPUART 121 #define CONFIG_LPUART_32B_REG 122 #define CFG_UART_MUX_MASK 0x6 123 #define CFG_UART_MUX_SHIFT 1 124 #define CFG_LPUART_EN 0x2 125 #endif 126 127 /* EEPROM */ 128 #define CONFIG_ID_EEPROM 129 #define CONFIG_SYS_I2C_EEPROM_NXID 130 #define CONFIG_SYS_EEPROM_BUS_NUM 0 131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 135 136 /* 137 * IFC Definitions 138 */ 139 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 140 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 141 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 142 CSPR_PORT_SIZE_16 | \ 143 CSPR_MSEL_NOR | \ 144 CSPR_V) 145 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 146 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 147 + 0x8000000) | \ 148 CSPR_PORT_SIZE_16 | \ 149 CSPR_MSEL_NOR | \ 150 CSPR_V) 151 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 152 153 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 154 CSOR_NOR_TRHZ_80) 155 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 156 FTIM0_NOR_TEADC(0x5) | \ 157 FTIM0_NOR_TAVDS(0x6) | \ 158 FTIM0_NOR_TEAHC(0x5)) 159 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 160 FTIM1_NOR_TRAD_NOR(0x1a) | \ 161 FTIM1_NOR_TSEQRAD_NOR(0x13)) 162 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 163 FTIM2_NOR_TCH(0x8) | \ 164 FTIM2_NOR_TWPH(0xe) | \ 165 FTIM2_NOR_TWP(0x1c)) 166 #define CONFIG_SYS_NOR_FTIM3 0 167 168 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 172 173 #define CONFIG_SYS_FLASH_EMPTY_INFO 174 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 175 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 176 177 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 178 #define CONFIG_SYS_WRITE_SWAPPED_DATA 179 180 /* 181 * NAND Flash Definitions 182 */ 183 #define CONFIG_NAND_FSL_IFC 184 185 #define CONFIG_SYS_NAND_BASE 0x7e800000 186 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 187 188 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 189 190 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 191 | CSPR_PORT_SIZE_8 \ 192 | CSPR_MSEL_NAND \ 193 | CSPR_V) 194 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 195 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 196 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 197 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 198 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 199 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 200 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 201 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 202 203 #define CONFIG_SYS_NAND_ONFI_DETECTION 204 205 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 206 FTIM0_NAND_TWP(0x18) | \ 207 FTIM0_NAND_TWCHT(0x7) | \ 208 FTIM0_NAND_TWH(0xa)) 209 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 210 FTIM1_NAND_TWBE(0x39) | \ 211 FTIM1_NAND_TRR(0xe) | \ 212 FTIM1_NAND_TRP(0x18)) 213 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 214 FTIM2_NAND_TREH(0xa) | \ 215 FTIM2_NAND_TWHRE(0x1e)) 216 #define CONFIG_SYS_NAND_FTIM3 0x0 217 218 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 219 #define CONFIG_SYS_MAX_NAND_DEVICE 1 220 #define CONFIG_MTD_NAND_VERIFY_WRITE 221 222 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 223 #endif 224 225 #ifdef CONFIG_NAND_BOOT 226 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 228 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 229 #endif 230 231 #if defined(CONFIG_TFABOOT) || \ 232 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 233 #define CONFIG_QIXIS_I2C_ACCESS 234 #define CONFIG_SYS_I2C_EARLY_INIT 235 #endif 236 237 /* 238 * QIXIS Definitions 239 */ 240 #define CONFIG_FSL_QIXIS 241 242 #ifdef CONFIG_FSL_QIXIS 243 #define QIXIS_BASE 0x7fb00000 244 #define QIXIS_BASE_PHYS QIXIS_BASE 245 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 246 #define QIXIS_LBMAP_SWITCH 6 247 #define QIXIS_LBMAP_MASK 0x0f 248 #define QIXIS_LBMAP_SHIFT 0 249 #define QIXIS_LBMAP_DFLTBANK 0x00 250 #define QIXIS_LBMAP_ALTBANK 0x04 251 #define QIXIS_LBMAP_NAND 0x09 252 #define QIXIS_LBMAP_SD 0x00 253 #define QIXIS_LBMAP_SD_QSPI 0xff 254 #define QIXIS_LBMAP_QSPI 0xff 255 #define QIXIS_RCW_SRC_NAND 0x110 256 #define QIXIS_RCW_SRC_SD 0x040 257 #define QIXIS_RCW_SRC_QSPI 0x045 258 #define QIXIS_RST_CTL_RESET 0x41 259 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 260 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 261 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 262 263 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 264 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 265 CSPR_PORT_SIZE_8 | \ 266 CSPR_MSEL_GPCM | \ 267 CSPR_V) 268 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 269 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 270 CSOR_NOR_NOR_MODE_AVD_NOR | \ 271 CSOR_NOR_TRHZ_80) 272 273 /* 274 * QIXIS Timing parameters for IFC GPCM 275 */ 276 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 277 FTIM0_GPCM_TEADC(0x20) | \ 278 FTIM0_GPCM_TEAHC(0x10)) 279 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 280 FTIM1_GPCM_TRAD(0x1f)) 281 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 282 FTIM2_GPCM_TCH(0x8) | \ 283 FTIM2_GPCM_TWP(0xf0)) 284 #define CONFIG_SYS_FPGA_FTIM3 0x0 285 #endif 286 287 #ifdef CONFIG_TFABOOT 288 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 289 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 290 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 291 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 292 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 293 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 294 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 295 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 296 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 297 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 298 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 305 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 306 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 307 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 308 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 309 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 310 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 311 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 312 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 313 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 314 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 315 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 316 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 317 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 318 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 319 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 320 #else 321 #ifdef CONFIG_NAND_BOOT 322 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 323 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 324 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 325 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 326 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 327 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 328 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 329 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 330 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 331 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 332 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 333 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 334 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 335 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 336 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 337 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 338 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 339 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 340 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 347 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 348 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 349 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 350 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 351 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 352 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 353 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 354 #else 355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 372 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 373 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 374 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 375 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 376 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 377 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 378 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 379 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 380 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 381 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 382 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 383 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 384 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 385 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 386 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 387 #endif 388 #endif 389 390 /* 391 * I2C bus multiplexer 392 */ 393 #define I2C_MUX_PCA_ADDR_PRI 0x77 394 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 395 #define I2C_RETIMER_ADDR 0x18 396 #define I2C_MUX_CH_DEFAULT 0x8 397 #define I2C_MUX_CH_CH7301 0xC 398 #define I2C_MUX_CH5 0xD 399 #define I2C_MUX_CH6 0xE 400 #define I2C_MUX_CH7 0xF 401 402 #define I2C_MUX_CH_VOL_MONITOR 0xa 403 404 /* Voltage monitor on channel 2*/ 405 #define I2C_VOL_MONITOR_ADDR 0x40 406 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 407 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 408 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 409 410 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 411 #ifndef CONFIG_SPL_BUILD 412 #define CONFIG_VID 413 #endif 414 #define CONFIG_VOL_MONITOR_IR36021_SET 415 #define CONFIG_VOL_MONITOR_INA220 416 /* The lowest and highest voltage allowed for LS1046AQDS */ 417 #define VDD_MV_MIN 819 418 #define VDD_MV_MAX 1212 419 420 /* 421 * Miscellaneous configurable options 422 */ 423 424 #define CONFIG_SYS_MEMTEST_START 0x80000000 425 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 426 427 #define CONFIG_SYS_HZ 1000 428 429 #define CONFIG_SYS_INIT_SP_OFFSET \ 430 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 431 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 433 434 /* 435 * Environment 436 */ 437 #define CONFIG_ENV_OVERWRITE 438 439 #ifdef CONFIG_TFABOOT 440 #define CONFIG_SYS_MMC_ENV_DEV 0 441 442 #define CONFIG_ENV_SIZE 0x2000 443 #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ 444 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) 445 #define CONFIG_ENV_SECT_SIZE 0x20000 446 #else 447 #ifdef CONFIG_NAND_BOOT 448 #define CONFIG_ENV_SIZE 0x2000 449 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 450 #elif defined(CONFIG_SD_BOOT) 451 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 452 #define CONFIG_SYS_MMC_ENV_DEV 0 453 #define CONFIG_ENV_SIZE 0x2000 454 #elif defined(CONFIG_QSPI_BOOT) 455 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 456 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 457 #define CONFIG_ENV_SECT_SIZE 0x10000 458 #else 459 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 460 #define CONFIG_ENV_SECT_SIZE 0x20000 461 #define CONFIG_ENV_SIZE 0x20000 462 #endif 463 #endif 464 465 #define CONFIG_CMDLINE_TAG 466 467 #undef CONFIG_BOOTCOMMAND 468 #ifdef CONFIG_TFABOOT 469 #define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 470 "e0000 f00000 && bootm $kernel_load" 471 #define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 472 "$kernel_size && bootm $kernel_load" 473 #define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \ 474 "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load" 475 #else 476 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 477 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 478 "e0000 f00000 && bootm $kernel_load" 479 #else 480 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 481 "$kernel_size && bootm $kernel_load" 482 #endif 483 #endif 484 485 #include <asm/fsl_secure_boot.h> 486 487 #endif /* __LS1046AQDS_H__ */ 488