1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046AQDS_H__ 8 #define __LS1046AQDS_H__ 9 10 #include "ls1046a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40100000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #ifndef CONFIG_SPL 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #endif 44 45 #define CONFIG_DDR_ECC 46 #ifdef CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 51 /* DSPI */ 52 #ifdef CONFIG_FSL_DSPI 53 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 54 #define CONFIG_SPI_FLASH_SST /* cs1 */ 55 #define CONFIG_SPI_FLASH_EON /* cs2 */ 56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 57 #define CONFIG_SF_DEFAULT_BUS 1 58 #define CONFIG_SF_DEFAULT_CS 0 59 #endif 60 #endif 61 62 /* QSPI */ 63 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 64 #ifdef CONFIG_FSL_QSPI 65 #define CONFIG_SPI_FLASH_SPANSION 66 #define FSL_QSPI_FLASH_SIZE (1 << 24) 67 #define FSL_QSPI_FLASH_NUM 2 68 #endif 69 #endif 70 71 #ifdef CONFIG_SYS_DPAA_FMAN 72 #define CONFIG_FMAN_ENET 73 #define CONFIG_PHY_VITESSE 74 #define CONFIG_PHY_REALTEK 75 #define CONFIG_PHYLIB_10G 76 #define RGMII_PHY1_ADDR 0x1 77 #define RGMII_PHY2_ADDR 0x2 78 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 79 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 80 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 81 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 82 /* PHY address on QSGMII riser card on slot 2 */ 83 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 84 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 85 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 86 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 87 #endif 88 89 #ifdef CONFIG_RAMBOOT_PBL 90 #define CONFIG_SYS_FSL_PBL_PBI \ 91 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg 92 #endif 93 94 #ifdef CONFIG_NAND_BOOT 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg 97 #endif 98 99 #ifdef CONFIG_SD_BOOT 100 #ifdef CONFIG_SD_BOOT_QSPI 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg 103 #else 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg 106 #endif 107 #endif 108 109 /* IFC */ 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 111 #define CONFIG_FSL_IFC 112 /* 113 * CONFIG_SYS_FLASH_BASE has the final address (core view) 114 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 115 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 116 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 117 */ 118 #define CONFIG_SYS_FLASH_BASE 0x60000000 119 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 121 122 #ifdef CONFIG_MTD_NOR_FLASH 123 #define CONFIG_FLASH_CFI_DRIVER 124 #define CONFIG_SYS_FLASH_CFI 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 126 #define CONFIG_SYS_FLASH_QUIET_TEST 127 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 128 #endif 129 #endif 130 131 /* LPUART */ 132 #ifdef CONFIG_LPUART 133 #define CONFIG_LPUART_32B_REG 134 #define CFG_UART_MUX_MASK 0x6 135 #define CFG_UART_MUX_SHIFT 1 136 #define CFG_LPUART_EN 0x2 137 #endif 138 139 /* EEPROM */ 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_SYS_EEPROM_BUS_NUM 0 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 147 148 /* 149 * IFC Definitions 150 */ 151 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 152 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 153 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 154 CSPR_PORT_SIZE_16 | \ 155 CSPR_MSEL_NOR | \ 156 CSPR_V) 157 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 158 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 159 + 0x8000000) | \ 160 CSPR_PORT_SIZE_16 | \ 161 CSPR_MSEL_NOR | \ 162 CSPR_V) 163 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 164 165 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 166 CSOR_NOR_TRHZ_80) 167 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 168 FTIM0_NOR_TEADC(0x5) | \ 169 FTIM0_NOR_TAVDS(0x6) | \ 170 FTIM0_NOR_TEAHC(0x5)) 171 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 172 FTIM1_NOR_TRAD_NOR(0x1a) | \ 173 FTIM1_NOR_TSEQRAD_NOR(0x13)) 174 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 175 FTIM2_NOR_TCH(0x8) | \ 176 FTIM2_NOR_TWPH(0xe) | \ 177 FTIM2_NOR_TWP(0x1c)) 178 #define CONFIG_SYS_NOR_FTIM3 0 179 180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 184 185 #define CONFIG_SYS_FLASH_EMPTY_INFO 186 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 187 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 188 189 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 190 #define CONFIG_SYS_WRITE_SWAPPED_DATA 191 192 /* 193 * NAND Flash Definitions 194 */ 195 #define CONFIG_NAND_FSL_IFC 196 197 #define CONFIG_SYS_NAND_BASE 0x7e800000 198 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 199 200 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 201 202 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 203 | CSPR_PORT_SIZE_8 \ 204 | CSPR_MSEL_NAND \ 205 | CSPR_V) 206 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 207 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 208 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 209 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 210 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 211 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 212 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 213 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 214 215 #define CONFIG_SYS_NAND_ONFI_DETECTION 216 217 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 218 FTIM0_NAND_TWP(0x18) | \ 219 FTIM0_NAND_TWCHT(0x7) | \ 220 FTIM0_NAND_TWH(0xa)) 221 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 222 FTIM1_NAND_TWBE(0x39) | \ 223 FTIM1_NAND_TRR(0xe) | \ 224 FTIM1_NAND_TRP(0x18)) 225 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 226 FTIM2_NAND_TREH(0xa) | \ 227 FTIM2_NAND_TWHRE(0x1e)) 228 #define CONFIG_SYS_NAND_FTIM3 0x0 229 230 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 231 #define CONFIG_SYS_MAX_NAND_DEVICE 1 232 #define CONFIG_MTD_NAND_VERIFY_WRITE 233 234 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) 235 #endif 236 237 #ifdef CONFIG_NAND_BOOT 238 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 241 #endif 242 243 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 244 #define CONFIG_QIXIS_I2C_ACCESS 245 #define CONFIG_SYS_I2C_EARLY_INIT 246 #endif 247 248 /* 249 * QIXIS Definitions 250 */ 251 #define CONFIG_FSL_QIXIS 252 253 #ifdef CONFIG_FSL_QIXIS 254 #define QIXIS_BASE 0x7fb00000 255 #define QIXIS_BASE_PHYS QIXIS_BASE 256 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 257 #define QIXIS_LBMAP_SWITCH 6 258 #define QIXIS_LBMAP_MASK 0x0f 259 #define QIXIS_LBMAP_SHIFT 0 260 #define QIXIS_LBMAP_DFLTBANK 0x00 261 #define QIXIS_LBMAP_ALTBANK 0x04 262 #define QIXIS_LBMAP_NAND 0x09 263 #define QIXIS_LBMAP_SD 0x00 264 #define QIXIS_LBMAP_SD_QSPI 0xff 265 #define QIXIS_LBMAP_QSPI 0xff 266 #define QIXIS_RCW_SRC_NAND 0x110 267 #define QIXIS_RCW_SRC_SD 0x040 268 #define QIXIS_RCW_SRC_QSPI 0x045 269 #define QIXIS_RST_CTL_RESET 0x41 270 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 271 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 272 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 273 274 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 275 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 276 CSPR_PORT_SIZE_8 | \ 277 CSPR_MSEL_GPCM | \ 278 CSPR_V) 279 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 280 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 281 CSOR_NOR_NOR_MODE_AVD_NOR | \ 282 CSOR_NOR_TRHZ_80) 283 284 /* 285 * QIXIS Timing parameters for IFC GPCM 286 */ 287 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 288 FTIM0_GPCM_TEADC(0x20) | \ 289 FTIM0_GPCM_TEAHC(0x10)) 290 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 291 FTIM1_GPCM_TRAD(0x1f)) 292 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 293 FTIM2_GPCM_TCH(0x8) | \ 294 FTIM2_GPCM_TWP(0xf0)) 295 #define CONFIG_SYS_FPGA_FTIM3 0x0 296 #endif 297 298 #ifdef CONFIG_NAND_BOOT 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 324 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 325 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 326 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 327 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 328 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 329 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 330 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 331 #else 332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 349 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 357 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 358 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 359 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 360 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 361 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 362 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 363 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 364 #endif 365 366 /* 367 * I2C bus multiplexer 368 */ 369 #define I2C_MUX_PCA_ADDR_PRI 0x77 370 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 371 #define I2C_RETIMER_ADDR 0x18 372 #define I2C_MUX_CH_DEFAULT 0x8 373 #define I2C_MUX_CH_CH7301 0xC 374 #define I2C_MUX_CH5 0xD 375 #define I2C_MUX_CH6 0xE 376 #define I2C_MUX_CH7 0xF 377 378 #define I2C_MUX_CH_VOL_MONITOR 0xa 379 380 /* Voltage monitor on channel 2*/ 381 #define I2C_VOL_MONITOR_ADDR 0x40 382 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 383 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 384 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 385 386 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" 387 #ifndef CONFIG_SPL_BUILD 388 #define CONFIG_VID 389 #endif 390 #define CONFIG_VOL_MONITOR_IR36021_SET 391 #define CONFIG_VOL_MONITOR_INA220 392 /* The lowest and highest voltage allowed for LS1046AQDS */ 393 #define VDD_MV_MIN 819 394 #define VDD_MV_MAX 1212 395 396 /* 397 * Miscellaneous configurable options 398 */ 399 #define CONFIG_MISC_INIT_R 400 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 401 #define CONFIG_AUTO_COMPLETE 402 403 #define CONFIG_SYS_MEMTEST_START 0x80000000 404 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 405 406 #define CONFIG_SYS_HZ 1000 407 408 #define CONFIG_SYS_INIT_SP_OFFSET \ 409 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 410 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 412 413 /* 414 * Environment 415 */ 416 #define CONFIG_ENV_OVERWRITE 417 418 #ifdef CONFIG_NAND_BOOT 419 #define CONFIG_ENV_SIZE 0x2000 420 #define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 421 #elif defined(CONFIG_SD_BOOT) 422 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 423 #define CONFIG_SYS_MMC_ENV_DEV 0 424 #define CONFIG_ENV_SIZE 0x2000 425 #elif defined(CONFIG_QSPI_BOOT) 426 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 427 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 428 #define CONFIG_ENV_SECT_SIZE 0x10000 429 #else 430 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 431 #define CONFIG_ENV_SECT_SIZE 0x20000 432 #define CONFIG_ENV_SIZE 0x20000 433 #endif 434 435 #define CONFIG_CMDLINE_TAG 436 437 #undef CONFIG_BOOTCOMMAND 438 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 439 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 440 "e0000 f00000 && bootm $kernel_load" 441 #else 442 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 443 "$kernel_size && bootm $kernel_load" 444 #endif 445 446 #include <asm/fsl_secure_boot.h> 447 448 #endif /* __LS1046AQDS_H__ */ 449