1 /*
2  * Copyright 2016 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_MP
13 #define CONFIG_SYS_FSL_CLK
14 #define CONFIG_GICV2
15 
16 #include <asm/arch/config.h>
17 
18 /* Link Definitions */
19 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
20 
21 #define CONFIG_SUPPORT_RAW_INITRD
22 
23 #define CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_BOARD_EARLY_INIT_F	1
25 
26 #define CONFIG_VERY_BIG_RAM
27 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
29 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
30 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
31 
32 #define CPU_RELEASE_ADDR               secondary_boot_func
33 
34 /* Generic Timer Definitions */
35 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
36 
37 /* Size of malloc() pool */
38 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
39 
40 /* Serial Port */
41 #define CONFIG_CONS_INDEX		1
42 #define CONFIG_SYS_NS16550_SERIAL
43 #define CONFIG_SYS_NS16550_REG_SIZE	1
44 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
45 
46 #define CONFIG_BAUDRATE			115200
47 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
48 
49 /* SD boot SPL */
50 #ifdef CONFIG_SD_BOOT
51 #define CONFIG_SPL_FRAMEWORK
52 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
53 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
54 #define CONFIG_SPL_LIBCOMMON_SUPPORT
55 #define CONFIG_SPL_LIBGENERIC_SUPPORT
56 #define CONFIG_SPL_ENV_SUPPORT
57 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
58 #define CONFIG_SPL_WATCHDOG_SUPPORT
59 #define CONFIG_SPL_I2C_SUPPORT
60 #define CONFIG_SPL_SERIAL_SUPPORT
61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
62 
63 #define CONFIG_SPL_MMC_SUPPORT
64 #define CONFIG_SPL_TEXT_BASE		0x10000000
65 #define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
66 #define CONFIG_SPL_STACK		0x10020000
67 #define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
68 #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
69 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
70 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
71 					CONFIG_SPL_BSS_MAX_SIZE)
72 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
73 #define CONFIG_SYS_MONITOR_LEN		0xa0000
74 #endif
75 
76 /* NAND SPL */
77 #ifdef CONFIG_NAND_BOOT
78 #define CONFIG_SPL_PBL_PAD
79 #define CONFIG_SPL_FRAMEWORK
80 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
81 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
82 #define CONFIG_SPL_LIBCOMMON_SUPPORT
83 #define CONFIG_SPL_LIBGENERIC_SUPPORT
84 #define CONFIG_SPL_ENV_SUPPORT
85 #define CONFIG_SPL_WATCHDOG_SUPPORT
86 #define CONFIG_SPL_I2C_SUPPORT
87 #define CONFIG_SPL_SERIAL_SUPPORT
88 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
89 
90 #define CONFIG_SPL_NAND_SUPPORT
91 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
92 #define CONFIG_SPL_TEXT_BASE		0x10000000
93 #define CONFIG_SPL_MAX_SIZE		0x1d000		/* 116 KiB */
94 #define CONFIG_SPL_STACK		0x1001f000
95 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
96 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
97 
98 #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
99 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
100 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
101 					CONFIG_SPL_BSS_MAX_SIZE)
102 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
103 #define CONFIG_SYS_MONITOR_LEN		0xa0000
104 #endif
105 
106 /* I2C */
107 #define CONFIG_SYS_I2C
108 #define CONFIG_SYS_I2C_MXC
109 #define CONFIG_SYS_I2C_MXC_I2C1
110 #define CONFIG_SYS_I2C_MXC_I2C2
111 #define CONFIG_SYS_I2C_MXC_I2C3
112 #define CONFIG_SYS_I2C_MXC_I2C4
113 
114 /* Command line configuration */
115 #define CONFIG_CMD_ENV
116 
117 /* MMC */
118 #define CONFIG_MMC
119 #ifdef CONFIG_MMC
120 #define CONFIG_FSL_ESDHC
121 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
122 #define CONFIG_GENERIC_MMC
123 #define CONFIG_DOS_PARTITION
124 #endif
125 
126 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
127 
128 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
129 
130 /* FMan ucode */
131 #define CONFIG_SYS_DPAA_FMAN
132 #ifdef CONFIG_SYS_DPAA_FMAN
133 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
134 
135 #ifdef CONFIG_SD_BOOT
136 /*
137  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
138  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
139  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
140  */
141 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
142 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
143 #elif defined(CONFIG_QSPI_BOOT)
144 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
145 #define CONFIG_SYS_FMAN_FW_ADDR		0x40300000
146 #define CONFIG_ENV_SPI_BUS		0
147 #define CONFIG_ENV_SPI_CS		0
148 #define CONFIG_ENV_SPI_MAX_HZ		1000000
149 #define CONFIG_ENV_SPI_MODE		0x03
150 #elif defined(CONFIG_NAND_BOOT)
151 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
152 #define CONFIG_SYS_FMAN_FW_ADDR		(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
153 #else
154 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
155 #define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
156 #endif
157 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
158 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
159 #endif
160 
161 /* Miscellaneous configurable options */
162 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
163 #define CONFIG_ARCH_EARLY_INIT_R
164 #define CONFIG_BOARD_LATE_INIT
165 
166 #define CONFIG_HWCONFIG
167 #define HWCONFIG_BUFFER_SIZE		128
168 
169 /* Initial environment variables */
170 #define CONFIG_EXTRA_ENV_SETTINGS		\
171 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
172 	"loadaddr=0x80100000\0"			\
173 	"ramdisk_addr=0x800000\0"		\
174 	"ramdisk_size=0x2000000\0"		\
175 	"fdt_high=0xffffffffffffffff\0"		\
176 	"initrd_high=0xffffffffffffffff\0"	\
177 	"kernel_start=0x1000000\0"		\
178 	"kernel_load=0xa0000000\0"		\
179 	"kernel_size=0x2800000\0"		\
180 	"console=ttyS0,115200\0"                \
181 		MTDPARTS_DEFAULT "\0"
182 
183 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
184 					"earlycon=uart8250,mmio,0x21c0500 " \
185 					MTDPARTS_DEFAULT
186 /* Monitor Command Prompt */
187 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
188 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
189 					sizeof(CONFIG_SYS_PROMPT) + 16)
190 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
191 #define CONFIG_SYS_LONGHELP
192 #define CONFIG_CMDLINE_EDITING		1
193 #define CONFIG_AUTO_COMPLETE
194 #define CONFIG_SYS_MAXARGS		64	/* max command args */
195 
196 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
197 
198 /* Hash command with SHA acceleration supported in hardware */
199 #ifdef CONFIG_FSL_CAAM
200 #define CONFIG_CMD_HASH
201 #define CONFIG_SHA_HW_ACCEL
202 #endif
203 
204 #endif /* __LS1046A_COMMON_H */
205