1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_QBMAN 13 #define SPL_NO_FMAN 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_QSPI 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #endif 20 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 21 #define SPL_NO_MMC 22 #endif 23 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) 24 #define SPL_NO_IFC 25 #endif 26 27 #define CONFIG_REMAKE_ELF 28 #define CONFIG_FSL_LAYERSCAPE 29 #define CONFIG_MP 30 #define CONFIG_GICV2 31 32 #include <asm/arch/config.h> 33 #include <asm/arch/stream_id_lsch2.h> 34 35 /* Link Definitions */ 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 37 38 #define CONFIG_SKIP_LOWLEVEL_INIT 39 40 #define CONFIG_VERY_BIG_RAM 41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 45 46 #define CPU_RELEASE_ADDR secondary_boot_func 47 48 /* Generic Timer Definitions */ 49 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 50 51 /* Size of malloc() pool */ 52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 53 54 /* Serial Port */ 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE 1 57 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 58 59 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 60 61 /* SD boot SPL */ 62 #ifdef CONFIG_SD_BOOT 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 #define CONFIG_SPL_LIBCOMMON_SUPPORT 65 #define CONFIG_SPL_LIBGENERIC_SUPPORT 66 #define CONFIG_SPL_ENV_SUPPORT 67 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 68 #define CONFIG_SPL_WATCHDOG_SUPPORT 69 #define CONFIG_SPL_I2C_SUPPORT 70 #define CONFIG_SPL_SERIAL_SUPPORT 71 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 72 73 #define CONFIG_SPL_MMC_SUPPORT 74 #define CONFIG_SPL_TEXT_BASE 0x10000000 75 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 76 #define CONFIG_SPL_STACK 0x10020000 77 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 78 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 79 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 80 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 81 CONFIG_SPL_BSS_MAX_SIZE) 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 84 #ifdef CONFIG_SECURE_BOOT 85 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 86 /* 87 * HDR would be appended at end of image and copied to DDR along 88 * with U-Boot image. Here u-boot max. size is 512K. So if binary 89 * size increases then increase this size in case of secure boot as 90 * it uses raw u-boot image instead of fit image. 91 */ 92 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 93 #else 94 #define CONFIG_SYS_MONITOR_LEN 0x100000 95 #endif /* ifdef CONFIG_SECURE_BOOT */ 96 #endif 97 98 /* NAND SPL */ 99 #ifdef CONFIG_NAND_BOOT 100 #define CONFIG_SPL_PBL_PAD 101 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 102 #define CONFIG_SPL_LIBCOMMON_SUPPORT 103 #define CONFIG_SPL_LIBGENERIC_SUPPORT 104 #define CONFIG_SPL_ENV_SUPPORT 105 #define CONFIG_SPL_WATCHDOG_SUPPORT 106 #define CONFIG_SPL_I2C_SUPPORT 107 #define CONFIG_SPL_SERIAL_SUPPORT 108 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 109 110 #define CONFIG_SPL_NAND_SUPPORT 111 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 112 #define CONFIG_SPL_TEXT_BASE 0x10000000 113 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ 114 #define CONFIG_SPL_STACK 0x1001f000 115 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 116 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 117 118 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 119 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 120 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 121 CONFIG_SPL_BSS_MAX_SIZE) 122 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 123 #define CONFIG_SYS_MONITOR_LEN 0xa0000 124 #endif 125 126 /* I2C */ 127 #define CONFIG_SYS_I2C 128 #define CONFIG_SYS_I2C_MXC 129 #define CONFIG_SYS_I2C_MXC_I2C1 130 #define CONFIG_SYS_I2C_MXC_I2C2 131 #define CONFIG_SYS_I2C_MXC_I2C3 132 #define CONFIG_SYS_I2C_MXC_I2C4 133 134 /* PCIe */ 135 #define CONFIG_PCIE1 /* PCIE controller 1 */ 136 #define CONFIG_PCIE2 /* PCIE controller 2 */ 137 #define CONFIG_PCIE3 /* PCIE controller 3 */ 138 139 #ifdef CONFIG_PCI 140 #define CONFIG_PCI_SCAN_SHOW 141 #endif 142 143 /* SATA */ 144 #ifndef SPL_NO_SATA 145 #define CONFIG_SCSI_AHCI_PLAT 146 147 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 148 149 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 150 #define CONFIG_SYS_SCSI_MAX_LUN 1 151 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 152 CONFIG_SYS_SCSI_MAX_LUN) 153 #endif 154 155 /* Command line configuration */ 156 157 /* MMC */ 158 #ifndef SPL_NO_MMC 159 #ifdef CONFIG_MMC 160 #define CONFIG_FSL_ESDHC 161 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 162 #endif 163 #endif 164 165 /* FMan ucode */ 166 #ifndef SPL_NO_FMAN 167 #define CONFIG_SYS_DPAA_FMAN 168 #ifdef CONFIG_SYS_DPAA_FMAN 169 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 170 #endif 171 172 #ifdef CONFIG_SD_BOOT 173 /* 174 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 175 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 176 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). 177 */ 178 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 179 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 180 #elif defined(CONFIG_QSPI_BOOT) 181 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 182 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 183 #define CONFIG_ENV_SPI_BUS 0 184 #define CONFIG_ENV_SPI_CS 0 185 #define CONFIG_ENV_SPI_MAX_HZ 1000000 186 #define CONFIG_ENV_SPI_MODE 0x03 187 #elif defined(CONFIG_NAND_BOOT) 188 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 189 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) 190 #else 191 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 192 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 193 #endif 194 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 195 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 196 #endif 197 198 /* Miscellaneous configurable options */ 199 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 200 201 #define CONFIG_HWCONFIG 202 #define HWCONFIG_BUFFER_SIZE 128 203 204 #ifndef CONFIG_SPL_BUILD 205 #define BOOT_TARGET_DEVICES(func) \ 206 func(SCSI, scsi, 0) \ 207 func(MMC, mmc, 0) \ 208 func(USB, usb, 0) 209 #include <config_distro_bootcmd.h> 210 #endif 211 212 #ifndef SPL_NO_MISC 213 /* Initial environment variables */ 214 #define CONFIG_EXTRA_ENV_SETTINGS \ 215 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 216 "ramdisk_addr=0x800000\0" \ 217 "ramdisk_size=0x2000000\0" \ 218 "fdt_high=0xffffffffffffffff\0" \ 219 "initrd_high=0xffffffffffffffff\0" \ 220 "fdt_addr=0x64f00000\0" \ 221 "kernel_addr=0x65000000\0" \ 222 "scriptaddr=0x80000000\0" \ 223 "scripthdraddr=0x80080000\0" \ 224 "fdtheader_addr_r=0x80100000\0" \ 225 "kernelheader_addr_r=0x80200000\0" \ 226 "load_addr=0xa0000000\0" \ 227 "kernel_addr_r=0x81000000\0" \ 228 "fdt_addr_r=0x90000000\0" \ 229 "ramdisk_addr_r=0xa0000000\0" \ 230 "kernel_start=0x1000000\0" \ 231 "kernelheader_start=0x800000\0" \ 232 "kernel_load=0xa0000000\0" \ 233 "kernel_size=0x2800000\0" \ 234 "kernelheader_size=0x40000\0" \ 235 "kernel_addr_sd=0x8000\0" \ 236 "kernel_size_sd=0x14000\0" \ 237 "kernelhdr_addr_sd=0x4000\0" \ 238 "kernelhdr_size_sd=0x10\0" \ 239 "console=ttyS0,115200\0" \ 240 CONFIG_MTDPARTS_DEFAULT "\0" \ 241 BOOTENV \ 242 "boot_scripts=ls1046ardb_boot.scr\0" \ 243 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ 244 "scan_dev_for_boot_part=" \ 245 "part list ${devtype} ${devnum} devplist; " \ 246 "env exists devplist || setenv devplist 1; " \ 247 "for distro_bootpart in ${devplist}; do " \ 248 "if fstype ${devtype} " \ 249 "${devnum}:${distro_bootpart} " \ 250 "bootfstype; then " \ 251 "run scan_dev_for_boot; " \ 252 "fi; " \ 253 "done\0" \ 254 "scan_dev_for_boot=" \ 255 "echo Scanning ${devtype} " \ 256 "${devnum}:${distro_bootpart}...; " \ 257 "for prefix in ${boot_prefixes}; do " \ 258 "run scan_dev_for_scripts; " \ 259 "done;" \ 260 "\0" \ 261 "boot_a_script=" \ 262 "load ${devtype} ${devnum}:${distro_bootpart} " \ 263 "${scriptaddr} ${prefix}${script}; " \ 264 "env exists secureboot && load ${devtype} " \ 265 "${devnum}:${distro_bootpart} " \ 266 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 267 "&& esbc_validate ${scripthdraddr};" \ 268 "source ${scriptaddr}\0" \ 269 "qspi_bootcmd=echo Trying load from qspi..;" \ 270 "sf probe && sf read $load_addr " \ 271 "$kernel_start $kernel_size; env exists secureboot " \ 272 "&& sf read $kernelheader_addr_r $kernelheader_start " \ 273 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 274 "bootm $load_addr#$board\0" \ 275 "sd_bootcmd=echo Trying load from SD ..;" \ 276 "mmcinfo; mmc read $load_addr " \ 277 "$kernel_addr_sd $kernel_size_sd && " \ 278 "env exists secureboot && mmc read $kernelheader_addr_r " \ 279 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 280 " && esbc_validate ${kernelheader_addr_r};" \ 281 "bootm $load_addr#$board\0" 282 283 #endif 284 285 /* Monitor Command Prompt */ 286 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 287 288 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 289 290 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 291 292 #include <asm/arch/soc.h> 293 294 #endif /* __LS1046A_COMMON_H */ 295