1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_QBMAN 13 #define SPL_NO_FMAN 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_QSPI 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #endif 20 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 21 #define SPL_NO_MMC 22 #endif 23 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) 24 #define SPL_NO_IFC 25 #endif 26 27 #define CONFIG_REMAKE_ELF 28 #define CONFIG_FSL_LAYERSCAPE 29 #define CONFIG_MP 30 #define CONFIG_GICV2 31 32 #include <asm/arch/config.h> 33 #include <asm/arch/stream_id_lsch2.h> 34 35 /* Link Definitions */ 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 37 38 #define CONFIG_SUPPORT_RAW_INITRD 39 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 47 48 #define CPU_RELEASE_ADDR secondary_boot_func 49 50 /* Generic Timer Definitions */ 51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 52 53 /* Size of malloc() pool */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 55 56 /* Serial Port */ 57 #define CONFIG_CONS_INDEX 1 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE 1 60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 61 62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 63 64 /* SD boot SPL */ 65 #ifdef CONFIG_SD_BOOT 66 #define CONFIG_SPL_FRAMEWORK 67 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 68 #define CONFIG_SPL_LIBCOMMON_SUPPORT 69 #define CONFIG_SPL_LIBGENERIC_SUPPORT 70 #define CONFIG_SPL_ENV_SUPPORT 71 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 72 #define CONFIG_SPL_WATCHDOG_SUPPORT 73 #define CONFIG_SPL_I2C_SUPPORT 74 #define CONFIG_SPL_SERIAL_SUPPORT 75 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 76 77 #define CONFIG_SPL_MMC_SUPPORT 78 #define CONFIG_SPL_TEXT_BASE 0x10000000 79 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 80 #define CONFIG_SPL_STACK 0x10020000 81 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 82 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 83 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 84 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 85 CONFIG_SPL_BSS_MAX_SIZE) 86 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 87 88 #ifdef CONFIG_SECURE_BOOT 89 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 90 /* 91 * HDR would be appended at end of image and copied to DDR along 92 * with U-Boot image. Here u-boot max. size is 512K. So if binary 93 * size increases then increase this size in case of secure boot as 94 * it uses raw u-boot image instead of fit image. 95 */ 96 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 97 #else 98 #define CONFIG_SYS_MONITOR_LEN 0x100000 99 #endif /* ifdef CONFIG_SECURE_BOOT */ 100 #endif 101 102 /* NAND SPL */ 103 #ifdef CONFIG_NAND_BOOT 104 #define CONFIG_SPL_PBL_PAD 105 #define CONFIG_SPL_FRAMEWORK 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SPL_LIBCOMMON_SUPPORT 108 #define CONFIG_SPL_LIBGENERIC_SUPPORT 109 #define CONFIG_SPL_ENV_SUPPORT 110 #define CONFIG_SPL_WATCHDOG_SUPPORT 111 #define CONFIG_SPL_I2C_SUPPORT 112 #define CONFIG_SPL_SERIAL_SUPPORT 113 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 114 115 #define CONFIG_SPL_NAND_SUPPORT 116 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 117 #define CONFIG_SPL_TEXT_BASE 0x10000000 118 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ 119 #define CONFIG_SPL_STACK 0x1001f000 120 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 121 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 122 123 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 124 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 125 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 126 CONFIG_SPL_BSS_MAX_SIZE) 127 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 128 #define CONFIG_SYS_MONITOR_LEN 0xa0000 129 #endif 130 131 /* I2C */ 132 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_I2C_MXC 134 #define CONFIG_SYS_I2C_MXC_I2C1 135 #define CONFIG_SYS_I2C_MXC_I2C2 136 #define CONFIG_SYS_I2C_MXC_I2C3 137 #define CONFIG_SYS_I2C_MXC_I2C4 138 139 /* PCIe */ 140 #define CONFIG_PCIE1 /* PCIE controller 1 */ 141 #define CONFIG_PCIE2 /* PCIE controller 2 */ 142 #define CONFIG_PCIE3 /* PCIE controller 3 */ 143 144 #ifdef CONFIG_PCI 145 #define CONFIG_PCI_SCAN_SHOW 146 #endif 147 148 /* Command line configuration */ 149 150 /* MMC */ 151 #ifndef SPL_NO_MMC 152 #ifdef CONFIG_MMC 153 #define CONFIG_FSL_ESDHC 154 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 155 #endif 156 #endif 157 158 #ifndef SPL_NO_QBMAN 159 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 160 #endif 161 162 /* FMan ucode */ 163 #ifndef SPL_NO_FMAN 164 #define CONFIG_SYS_DPAA_FMAN 165 #ifdef CONFIG_SYS_DPAA_FMAN 166 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 167 #endif 168 169 #ifdef CONFIG_SD_BOOT 170 /* 171 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 172 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 173 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). 174 */ 175 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 176 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 177 #elif defined(CONFIG_QSPI_BOOT) 178 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 179 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 180 #define CONFIG_ENV_SPI_BUS 0 181 #define CONFIG_ENV_SPI_CS 0 182 #define CONFIG_ENV_SPI_MAX_HZ 1000000 183 #define CONFIG_ENV_SPI_MODE 0x03 184 #elif defined(CONFIG_NAND_BOOT) 185 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 186 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #else 188 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 189 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 190 #endif 191 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 192 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 193 #endif 194 195 /* Miscellaneous configurable options */ 196 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 197 198 #define CONFIG_HWCONFIG 199 #define HWCONFIG_BUFFER_SIZE 128 200 201 #include <config_distro_defaults.h> 202 #ifndef CONFIG_SPL_BUILD 203 #define BOOT_TARGET_DEVICES(func) \ 204 func(MMC, mmc, 0) \ 205 func(USB, usb, 0) 206 #include <config_distro_bootcmd.h> 207 #endif 208 209 #ifndef SPL_NO_MISC 210 /* Initial environment variables */ 211 #define CONFIG_EXTRA_ENV_SETTINGS \ 212 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 213 "ramdisk_addr=0x800000\0" \ 214 "ramdisk_size=0x2000000\0" \ 215 "fdt_high=0xffffffffffffffff\0" \ 216 "initrd_high=0xffffffffffffffff\0" \ 217 "fdt_addr=0x64f00000\0" \ 218 "kernel_addr=0x65000000\0" \ 219 "scriptaddr=0x80000000\0" \ 220 "scripthdraddr=0x80080000\0" \ 221 "fdtheader_addr_r=0x80100000\0" \ 222 "kernelheader_addr_r=0x80200000\0" \ 223 "load_addr=0xa0000000\0" \ 224 "kernel_addr_r=0x81000000\0" \ 225 "fdt_addr_r=0x90000000\0" \ 226 "ramdisk_addr_r=0xa0000000\0" \ 227 "kernel_start=0x1000000\0" \ 228 "kernel_load=0xa0000000\0" \ 229 "kernel_size=0x2800000\0" \ 230 "console=ttyS0,115200\0" \ 231 MTDPARTS_DEFAULT "\0" \ 232 BOOTENV \ 233 "boot_scripts=ls1046ardb_boot.scr\0" \ 234 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ 235 "scan_dev_for_boot_part=" \ 236 "part list ${devtype} ${devnum} devplist; " \ 237 "env exists devplist || setenv devplist 1; " \ 238 "for distro_bootpart in ${devplist}; do " \ 239 "if fstype ${devtype} " \ 240 "${devnum}:${distro_bootpart} " \ 241 "bootfstype; then " \ 242 "run scan_dev_for_boot; " \ 243 "fi; " \ 244 "done\0" \ 245 "scan_dev_for_boot=" \ 246 "echo Scanning ${devtype} " \ 247 "${devnum}:${distro_bootpart}...; " \ 248 "for prefix in ${boot_prefixes}; do " \ 249 "run scan_dev_for_scripts; " \ 250 "done;" \ 251 "\0" \ 252 "boot_a_script=" \ 253 "load ${devtype} ${devnum}:${distro_bootpart} " \ 254 "${scriptaddr} ${prefix}${script}; " \ 255 "env exists secureboot && load ${devtype} " \ 256 "${devnum}:${distro_bootpart} " \ 257 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 258 "&& esbc_validate ${scripthdraddr};" \ 259 "source ${scriptaddr}\0" \ 260 "installer=load mmc 0:2 $load_addr " \ 261 "/flex_installer_arm64.itb; " \ 262 "bootm $load_addr#ls1046ardb\0" \ 263 "qspi_bootcmd=echo Trying load from qspi..;" \ 264 "sf probe && sf read $load_addr " \ 265 "$kernel_start $kernel_size && bootm $load_addr#$board\0" 266 267 #endif 268 269 /* Monitor Command Prompt */ 270 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 271 #define CONFIG_SYS_LONGHELP 272 273 #define CONFIG_AUTO_COMPLETE 274 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 275 276 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 277 278 #include <asm/arch/soc.h> 279 280 #endif /* __LS1046A_COMMON_H */ 281