1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1046A_COMMON_H 7 #define __LS1046A_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_QBMAN 12 #define SPL_NO_FMAN 13 #define SPL_NO_ENV 14 #define SPL_NO_MISC 15 #define SPL_NO_QSPI 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #endif 19 #if defined(CONFIG_SPL_BUILD) && \ 20 (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) 21 #define SPL_NO_MMC 22 #endif 23 #if defined(CONFIG_SPL_BUILD) && \ 24 !defined(CONFIG_SPL_FSL_LS_PPA) 25 #define SPL_NO_IFC 26 #endif 27 28 #define CONFIG_REMAKE_ELF 29 #define CONFIG_FSL_LAYERSCAPE 30 #define CONFIG_GICV2 31 32 #include <asm/arch/config.h> 33 #include <asm/arch/stream_id_lsch2.h> 34 35 /* Link Definitions */ 36 #ifdef CONFIG_TFABOOT 37 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 38 #else 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 40 #endif 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 49 50 #define CPU_RELEASE_ADDR secondary_boot_func 51 52 /* Generic Timer Definitions */ 53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 54 55 /* Size of malloc() pool */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 57 58 /* Serial Port */ 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE 1 61 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 62 63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 64 65 /* SD boot SPL */ 66 #ifdef CONFIG_SD_BOOT 67 #define CONFIG_SPL_TEXT_BASE 0x10000000 68 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 69 #define CONFIG_SPL_STACK 0x10020000 70 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 71 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 72 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 73 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 74 CONFIG_SPL_BSS_MAX_SIZE) 75 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 76 77 #ifdef CONFIG_SECURE_BOOT 78 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 79 /* 80 * HDR would be appended at end of image and copied to DDR along 81 * with U-Boot image. Here u-boot max. size is 512K. So if binary 82 * size increases then increase this size in case of secure boot as 83 * it uses raw u-boot image instead of fit image. 84 */ 85 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 86 #else 87 #define CONFIG_SYS_MONITOR_LEN 0x100000 88 #endif /* ifdef CONFIG_SECURE_BOOT */ 89 #endif 90 91 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) 92 #define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" 93 #define CONFIG_SPL_TEXT_BASE 0x10000000 94 #define CONFIG_SPL_MAX_SIZE 0x1f000 95 #define CONFIG_SPL_STACK 0x10020000 96 #define CONFIG_SPL_PAD_TO 0x20000 97 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 98 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 99 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 100 CONFIG_SPL_BSS_MAX_SIZE) 101 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 102 #define CONFIG_SYS_MONITOR_LEN 0x100000 103 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 104 #endif 105 106 /* NAND SPL */ 107 #ifdef CONFIG_NAND_BOOT 108 #define CONFIG_SPL_PBL_PAD 109 #define CONFIG_SPL_LIBCOMMON_SUPPORT 110 #define CONFIG_SPL_LIBGENERIC_SUPPORT 111 #define CONFIG_SPL_ENV_SUPPORT 112 #define CONFIG_SPL_WATCHDOG_SUPPORT 113 #define CONFIG_SPL_I2C_SUPPORT 114 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 115 116 #define CONFIG_SPL_NAND_SUPPORT 117 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 118 #define CONFIG_SPL_TEXT_BASE 0x10000000 119 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ 120 #define CONFIG_SPL_STACK 0x1001f000 121 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 123 124 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 125 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 126 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 127 CONFIG_SPL_BSS_MAX_SIZE) 128 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 129 #define CONFIG_SYS_MONITOR_LEN 0xa0000 130 #endif 131 132 /* I2C */ 133 #define CONFIG_SYS_I2C 134 135 /* PCIe */ 136 #define CONFIG_PCIE1 /* PCIE controller 1 */ 137 #define CONFIG_PCIE2 /* PCIE controller 2 */ 138 #define CONFIG_PCIE3 /* PCIE controller 3 */ 139 140 #ifdef CONFIG_PCI 141 #define CONFIG_PCI_SCAN_SHOW 142 #endif 143 144 /* SATA */ 145 #ifndef SPL_NO_SATA 146 #define CONFIG_SCSI_AHCI_PLAT 147 148 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 149 150 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 151 #define CONFIG_SYS_SCSI_MAX_LUN 1 152 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 153 CONFIG_SYS_SCSI_MAX_LUN) 154 #endif 155 156 /* Command line configuration */ 157 158 /* MMC */ 159 #ifndef SPL_NO_MMC 160 #ifdef CONFIG_MMC 161 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 162 #endif 163 #endif 164 165 /* FMan ucode */ 166 #ifndef SPL_NO_FMAN 167 #define CONFIG_SYS_DPAA_FMAN 168 #ifdef CONFIG_SYS_DPAA_FMAN 169 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 170 #endif 171 172 #ifdef CONFIG_TFABOOT 173 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000 174 #define CONFIG_ENV_SPI_BUS 0 175 #define CONFIG_ENV_SPI_CS 0 176 #define CONFIG_ENV_SPI_MAX_HZ 1000000 177 #define CONFIG_ENV_SPI_MODE 0x03 178 #else 179 #ifdef CONFIG_SD_BOOT 180 /* 181 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 182 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 183 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). 184 */ 185 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 186 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 187 #elif defined(CONFIG_QSPI_BOOT) 188 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 189 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 190 #define CONFIG_ENV_SPI_BUS 0 191 #define CONFIG_ENV_SPI_CS 0 192 #define CONFIG_ENV_SPI_MAX_HZ 1000000 193 #define CONFIG_ENV_SPI_MODE 0x03 194 #elif defined(CONFIG_NAND_BOOT) 195 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 196 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) 197 #else 198 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 199 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 200 #endif 201 #endif 202 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 203 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 204 #endif 205 206 /* Miscellaneous configurable options */ 207 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 208 209 #define CONFIG_HWCONFIG 210 #define HWCONFIG_BUFFER_SIZE 128 211 212 #ifndef CONFIG_SPL_BUILD 213 #define BOOT_TARGET_DEVICES(func) \ 214 func(SCSI, scsi, 0) \ 215 func(MMC, mmc, 0) \ 216 func(USB, usb, 0) 217 #include <config_distro_bootcmd.h> 218 #endif 219 220 #ifndef SPL_NO_MISC 221 /* Initial environment variables */ 222 #define CONFIG_EXTRA_ENV_SETTINGS \ 223 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 224 "ramdisk_addr=0x800000\0" \ 225 "ramdisk_size=0x2000000\0" \ 226 "fdt_high=0xffffffffffffffff\0" \ 227 "initrd_high=0xffffffffffffffff\0" \ 228 "fdt_addr=0x64f00000\0" \ 229 "kernel_addr=0x65000000\0" \ 230 "scriptaddr=0x80000000\0" \ 231 "scripthdraddr=0x80080000\0" \ 232 "fdtheader_addr_r=0x80100000\0" \ 233 "kernelheader_addr_r=0x80200000\0" \ 234 "load_addr=0xa0000000\0" \ 235 "kernel_addr_r=0x81000000\0" \ 236 "fdt_addr_r=0x90000000\0" \ 237 "ramdisk_addr_r=0xa0000000\0" \ 238 "kernel_start=0x1000000\0" \ 239 "kernelheader_start=0x800000\0" \ 240 "kernel_load=0xa0000000\0" \ 241 "kernel_size=0x2800000\0" \ 242 "kernelheader_size=0x40000\0" \ 243 "kernel_addr_sd=0x8000\0" \ 244 "kernel_size_sd=0x14000\0" \ 245 "kernelhdr_addr_sd=0x4000\0" \ 246 "kernelhdr_size_sd=0x10\0" \ 247 "console=ttyS0,115200\0" \ 248 CONFIG_MTDPARTS_DEFAULT "\0" \ 249 BOOTENV \ 250 "boot_scripts=ls1046ardb_boot.scr\0" \ 251 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ 252 "scan_dev_for_boot_part=" \ 253 "part list ${devtype} ${devnum} devplist; " \ 254 "env exists devplist || setenv devplist 1; " \ 255 "for distro_bootpart in ${devplist}; do " \ 256 "if fstype ${devtype} " \ 257 "${devnum}:${distro_bootpart} " \ 258 "bootfstype; then " \ 259 "run scan_dev_for_boot; " \ 260 "fi; " \ 261 "done\0" \ 262 "scan_dev_for_boot=" \ 263 "echo Scanning ${devtype} " \ 264 "${devnum}:${distro_bootpart}...; " \ 265 "for prefix in ${boot_prefixes}; do " \ 266 "run scan_dev_for_scripts; " \ 267 "done;" \ 268 "\0" \ 269 "boot_a_script=" \ 270 "load ${devtype} ${devnum}:${distro_bootpart} " \ 271 "${scriptaddr} ${prefix}${script}; " \ 272 "env exists secureboot && load ${devtype} " \ 273 "${devnum}:${distro_bootpart} " \ 274 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 275 "&& esbc_validate ${scripthdraddr};" \ 276 "source ${scriptaddr}\0" \ 277 "qspi_bootcmd=echo Trying load from qspi..;" \ 278 "sf probe && sf read $load_addr " \ 279 "$kernel_start $kernel_size; env exists secureboot " \ 280 "&& sf read $kernelheader_addr_r $kernelheader_start " \ 281 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 282 "bootm $load_addr#$board\0" \ 283 "sd_bootcmd=echo Trying load from SD ..;" \ 284 "mmcinfo; mmc read $load_addr " \ 285 "$kernel_addr_sd $kernel_size_sd && " \ 286 "env exists secureboot && mmc read $kernelheader_addr_r " \ 287 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 288 " && esbc_validate ${kernelheader_addr_r};" \ 289 "bootm $load_addr#$board\0" 290 291 #endif 292 293 /* Monitor Command Prompt */ 294 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 295 296 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 297 298 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 299 300 #include <asm/arch/soc.h> 301 302 #endif /* __LS1046A_COMMON_H */ 303