1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_MP 13 #define CONFIG_SYS_FSL_CLK 14 #define CONFIG_GICV2 15 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 21 #define CONFIG_SUPPORT_RAW_INITRD 22 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #define CONFIG_BOARD_EARLY_INIT_F 1 25 26 #define CONFIG_VERY_BIG_RAM 27 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 29 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 30 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 31 32 #define CPU_RELEASE_ADDR secondary_boot_func 33 34 /* Generic Timer Definitions */ 35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 36 37 /* Size of malloc() pool */ 38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 39 40 /* Serial Port */ 41 #define CONFIG_CONS_INDEX 1 42 #define CONFIG_SYS_NS16550_SERIAL 43 #define CONFIG_SYS_NS16550_REG_SIZE 1 44 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 45 46 #define CONFIG_BAUDRATE 115200 47 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 48 49 /* SD boot SPL */ 50 #ifdef CONFIG_SD_BOOT 51 #define CONFIG_SPL_FRAMEWORK 52 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 53 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 54 #define CONFIG_SPL_LIBCOMMON_SUPPORT 55 #define CONFIG_SPL_LIBGENERIC_SUPPORT 56 #define CONFIG_SPL_ENV_SUPPORT 57 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 58 #define CONFIG_SPL_WATCHDOG_SUPPORT 59 #define CONFIG_SPL_I2C_SUPPORT 60 #define CONFIG_SPL_SERIAL_SUPPORT 61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 62 63 #define CONFIG_SPL_MMC_SUPPORT 64 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x110 65 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 66 #define CONFIG_SPL_TEXT_BASE 0x10000000 67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 68 #define CONFIG_SPL_STACK 0x10020000 69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 73 CONFIG_SPL_BSS_MAX_SIZE) 74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 75 #define CONFIG_SYS_MONITOR_LEN 0xa0000 76 #endif 77 78 /* NAND SPL */ 79 #ifdef CONFIG_NAND_BOOT 80 #define CONFIG_SPL_PBL_PAD 81 #define CONFIG_SPL_FRAMEWORK 82 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 83 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 84 #define CONFIG_SPL_LIBCOMMON_SUPPORT 85 #define CONFIG_SPL_LIBGENERIC_SUPPORT 86 #define CONFIG_SPL_ENV_SUPPORT 87 #define CONFIG_SPL_WATCHDOG_SUPPORT 88 #define CONFIG_SPL_I2C_SUPPORT 89 #define CONFIG_SPL_SERIAL_SUPPORT 90 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 91 92 #define CONFIG_SPL_NAND_SUPPORT 93 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 94 #define CONFIG_SPL_TEXT_BASE 0x10000000 95 #define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ 96 #define CONFIG_SPL_STACK 0x1001f000 97 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 99 100 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 101 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 102 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 103 CONFIG_SPL_BSS_MAX_SIZE) 104 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 105 #define CONFIG_SYS_MONITOR_LEN 0xa0000 106 #endif 107 108 /* I2C */ 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_I2C_MXC 111 #define CONFIG_SYS_I2C_MXC_I2C1 112 #define CONFIG_SYS_I2C_MXC_I2C2 113 #define CONFIG_SYS_I2C_MXC_I2C3 114 #define CONFIG_SYS_I2C_MXC_I2C4 115 116 /* Command line configuration */ 117 #define CONFIG_CMD_ENV 118 119 /* MMC */ 120 #define CONFIG_MMC 121 #ifdef CONFIG_MMC 122 #define CONFIG_FSL_ESDHC 123 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 124 #define CONFIG_GENERIC_MMC 125 #define CONFIG_DOS_PARTITION 126 #endif 127 128 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 129 130 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 131 132 /* FMan ucode */ 133 #define CONFIG_SYS_DPAA_FMAN 134 #ifdef CONFIG_SYS_DPAA_FMAN 135 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 136 137 #ifdef CONFIG_SD_BOOT 138 /* 139 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 140 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 141 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 142 */ 143 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 144 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 145 #elif defined(CONFIG_QSPI_BOOT) 146 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 147 #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 148 #define CONFIG_ENV_SPI_BUS 0 149 #define CONFIG_ENV_SPI_CS 0 150 #define CONFIG_ENV_SPI_MAX_HZ 1000000 151 #define CONFIG_ENV_SPI_MODE 0x03 152 #elif defined(CONFIG_NAND_BOOT) 153 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 154 #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 155 #else 156 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 157 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 158 #endif 159 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 160 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 161 #endif 162 163 /* Miscellaneous configurable options */ 164 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 165 #define CONFIG_ARCH_EARLY_INIT_R 166 #define CONFIG_BOARD_LATE_INIT 167 168 #define CONFIG_HWCONFIG 169 #define HWCONFIG_BUFFER_SIZE 128 170 171 /* Initial environment variables */ 172 #define CONFIG_EXTRA_ENV_SETTINGS \ 173 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 174 "loadaddr=0x80100000\0" \ 175 "ramdisk_addr=0x800000\0" \ 176 "ramdisk_size=0x2000000\0" \ 177 "fdt_high=0xffffffffffffffff\0" \ 178 "initrd_high=0xffffffffffffffff\0" \ 179 "kernel_start=0x1000000\0" \ 180 "kernel_load=0xa0000000\0" \ 181 "kernel_size=0x2800000\0" \ 182 "console=ttyS0,115200\0" \ 183 MTDPARTS_DEFAULT "\0" 184 185 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 186 "earlycon=uart8250,mmio,0x21c0500 " \ 187 MTDPARTS_DEFAULT 188 /* Monitor Command Prompt */ 189 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 190 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 191 sizeof(CONFIG_SYS_PROMPT) + 16) 192 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 193 #define CONFIG_SYS_LONGHELP 194 #define CONFIG_CMDLINE_EDITING 1 195 #define CONFIG_AUTO_COMPLETE 196 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 197 198 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 199 200 /* Hash command with SHA acceleration supported in hardware */ 201 #ifdef CONFIG_FSL_CAAM 202 #define CONFIG_CMD_HASH 203 #define CONFIG_SHA_HW_ACCEL 204 #endif 205 206 #endif /* __LS1046A_COMMON_H */ 207