1 /*
2  * Copyright 2016 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_MP
13 #define CONFIG_GICV2
14 
15 #include <asm/arch/config.h>
16 
17 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
19 
20 #define CONFIG_SUPPORT_RAW_INITRD
21 
22 #define CONFIG_SKIP_LOWLEVEL_INIT
23 #define CONFIG_BOARD_EARLY_INIT_F	1
24 
25 #define CONFIG_VERY_BIG_RAM
26 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
28 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
29 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
30 
31 #define CPU_RELEASE_ADDR               secondary_boot_func
32 
33 /* Generic Timer Definitions */
34 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
35 
36 /* Size of malloc() pool */
37 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
38 
39 /* Serial Port */
40 #define CONFIG_CONS_INDEX		1
41 #define CONFIG_SYS_NS16550_SERIAL
42 #define CONFIG_SYS_NS16550_REG_SIZE	1
43 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
44 
45 #define CONFIG_BAUDRATE			115200
46 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
47 
48 /* SD boot SPL */
49 #ifdef CONFIG_SD_BOOT
50 #define CONFIG_SPL_FRAMEWORK
51 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
52 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
53 #define CONFIG_SPL_LIBCOMMON_SUPPORT
54 #define CONFIG_SPL_LIBGENERIC_SUPPORT
55 #define CONFIG_SPL_ENV_SUPPORT
56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
57 #define CONFIG_SPL_WATCHDOG_SUPPORT
58 #define CONFIG_SPL_I2C_SUPPORT
59 #define CONFIG_SPL_SERIAL_SUPPORT
60 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
61 
62 #define CONFIG_SPL_MMC_SUPPORT
63 #define CONFIG_SPL_TEXT_BASE		0x10000000
64 #define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
65 #define CONFIG_SPL_STACK		0x10020000
66 #define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
67 #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
68 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
69 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
70 					CONFIG_SPL_BSS_MAX_SIZE)
71 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
72 #define CONFIG_SYS_MONITOR_LEN		0xa0000
73 #endif
74 
75 /* NAND SPL */
76 #ifdef CONFIG_NAND_BOOT
77 #define CONFIG_SPL_PBL_PAD
78 #define CONFIG_SPL_FRAMEWORK
79 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
80 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
81 #define CONFIG_SPL_LIBCOMMON_SUPPORT
82 #define CONFIG_SPL_LIBGENERIC_SUPPORT
83 #define CONFIG_SPL_ENV_SUPPORT
84 #define CONFIG_SPL_WATCHDOG_SUPPORT
85 #define CONFIG_SPL_I2C_SUPPORT
86 #define CONFIG_SPL_SERIAL_SUPPORT
87 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
88 
89 #define CONFIG_SPL_NAND_SUPPORT
90 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
91 #define CONFIG_SPL_TEXT_BASE		0x10000000
92 #define CONFIG_SPL_MAX_SIZE		0x1d000		/* 116 KiB */
93 #define CONFIG_SPL_STACK		0x1001f000
94 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
95 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
96 
97 #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
98 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
99 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
100 					CONFIG_SPL_BSS_MAX_SIZE)
101 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
102 #define CONFIG_SYS_MONITOR_LEN		0xa0000
103 #endif
104 
105 /* I2C */
106 #define CONFIG_SYS_I2C
107 #define CONFIG_SYS_I2C_MXC
108 #define CONFIG_SYS_I2C_MXC_I2C1
109 #define CONFIG_SYS_I2C_MXC_I2C2
110 #define CONFIG_SYS_I2C_MXC_I2C3
111 #define CONFIG_SYS_I2C_MXC_I2C4
112 
113 /* Command line configuration */
114 #define CONFIG_CMD_ENV
115 
116 /* MMC */
117 #ifdef CONFIG_MMC
118 #define CONFIG_FSL_ESDHC
119 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
120 #define CONFIG_GENERIC_MMC
121 #define CONFIG_DOS_PARTITION
122 #endif
123 
124 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
125 
126 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
127 
128 /* FMan ucode */
129 #define CONFIG_SYS_DPAA_FMAN
130 #ifdef CONFIG_SYS_DPAA_FMAN
131 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
132 
133 #ifdef CONFIG_SD_BOOT
134 /*
135  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
136  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
137  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
138  */
139 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
140 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
141 #elif defined(CONFIG_QSPI_BOOT)
142 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
143 #define CONFIG_SYS_FMAN_FW_ADDR		0x40300000
144 #define CONFIG_ENV_SPI_BUS		0
145 #define CONFIG_ENV_SPI_CS		0
146 #define CONFIG_ENV_SPI_MAX_HZ		1000000
147 #define CONFIG_ENV_SPI_MODE		0x03
148 #elif defined(CONFIG_NAND_BOOT)
149 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
150 #define CONFIG_SYS_FMAN_FW_ADDR		(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
151 #else
152 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
153 #define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
154 #endif
155 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
156 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
157 #endif
158 
159 /* Miscellaneous configurable options */
160 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
161 #define CONFIG_ARCH_EARLY_INIT_R
162 
163 #define CONFIG_HWCONFIG
164 #define HWCONFIG_BUFFER_SIZE		128
165 
166 /* Initial environment variables */
167 #define CONFIG_EXTRA_ENV_SETTINGS		\
168 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
169 	"loadaddr=0x80100000\0"			\
170 	"ramdisk_addr=0x800000\0"		\
171 	"ramdisk_size=0x2000000\0"		\
172 	"fdt_high=0xffffffffffffffff\0"		\
173 	"initrd_high=0xffffffffffffffff\0"	\
174 	"kernel_start=0x1000000\0"		\
175 	"kernel_load=0xa0000000\0"		\
176 	"kernel_size=0x2800000\0"		\
177 	"console=ttyS0,115200\0"                \
178 		MTDPARTS_DEFAULT "\0"
179 
180 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
181 					"earlycon=uart8250,mmio,0x21c0500 " \
182 					MTDPARTS_DEFAULT
183 /* Monitor Command Prompt */
184 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
185 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
186 					sizeof(CONFIG_SYS_PROMPT) + 16)
187 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
188 #define CONFIG_SYS_LONGHELP
189 #define CONFIG_CMDLINE_EDITING		1
190 #define CONFIG_AUTO_COMPLETE
191 #define CONFIG_SYS_MAXARGS		64	/* max command args */
192 
193 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
194 
195 /* Hash command with SHA acceleration supported in hardware */
196 #ifdef CONFIG_FSL_CAAM
197 #define CONFIG_CMD_HASH
198 #define CONFIG_SHA_HW_ACCEL
199 #endif
200 
201 #endif /* __LS1046A_COMMON_H */
202