1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1046A_COMMON_H 8 #define __LS1046A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_QBMAN 13 #define SPL_NO_FMAN 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_QSPI 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #endif 20 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 21 #define SPL_NO_MMC 22 #endif 23 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) 24 #define SPL_NO_IFC 25 #endif 26 27 #define CONFIG_REMAKE_ELF 28 #define CONFIG_FSL_LAYERSCAPE 29 #define CONFIG_MP 30 #define CONFIG_GICV2 31 32 #include <asm/arch/config.h> 33 #include <asm/arch/stream_id_lsch2.h> 34 35 /* Link Definitions */ 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 37 38 #define CONFIG_SUPPORT_RAW_INITRD 39 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 47 48 #define CPU_RELEASE_ADDR secondary_boot_func 49 50 /* Generic Timer Definitions */ 51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 52 53 /* Size of malloc() pool */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 55 56 /* Serial Port */ 57 #define CONFIG_CONS_INDEX 1 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE 1 60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 61 62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 63 64 /* SD boot SPL */ 65 #ifdef CONFIG_SD_BOOT 66 #define CONFIG_SPL_FRAMEWORK 67 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 #define CONFIG_SPL_LIBCOMMON_SUPPORT 70 #define CONFIG_SPL_LIBGENERIC_SUPPORT 71 #define CONFIG_SPL_ENV_SUPPORT 72 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 73 #define CONFIG_SPL_WATCHDOG_SUPPORT 74 #define CONFIG_SPL_I2C_SUPPORT 75 #define CONFIG_SPL_SERIAL_SUPPORT 76 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 77 78 #define CONFIG_SPL_MMC_SUPPORT 79 #define CONFIG_SPL_TEXT_BASE 0x10000000 80 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ 81 #define CONFIG_SPL_STACK 0x10020000 82 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ 83 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 86 CONFIG_SPL_BSS_MAX_SIZE) 87 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 88 #define CONFIG_SYS_MONITOR_LEN 0xa0000 89 #endif 90 91 /* NAND SPL */ 92 #ifdef CONFIG_NAND_BOOT 93 #define CONFIG_SPL_PBL_PAD 94 #define CONFIG_SPL_FRAMEWORK 95 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 96 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 97 #define CONFIG_SPL_LIBCOMMON_SUPPORT 98 #define CONFIG_SPL_LIBGENERIC_SUPPORT 99 #define CONFIG_SPL_ENV_SUPPORT 100 #define CONFIG_SPL_WATCHDOG_SUPPORT 101 #define CONFIG_SPL_I2C_SUPPORT 102 #define CONFIG_SPL_SERIAL_SUPPORT 103 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 104 105 #define CONFIG_SPL_NAND_SUPPORT 106 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 107 #define CONFIG_SPL_TEXT_BASE 0x10000000 108 #define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ 109 #define CONFIG_SPL_STACK 0x1001f000 110 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 111 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 112 113 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 114 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 115 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 116 CONFIG_SPL_BSS_MAX_SIZE) 117 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 118 #define CONFIG_SYS_MONITOR_LEN 0xa0000 119 #endif 120 121 /* I2C */ 122 #define CONFIG_SYS_I2C 123 #define CONFIG_SYS_I2C_MXC 124 #define CONFIG_SYS_I2C_MXC_I2C1 125 #define CONFIG_SYS_I2C_MXC_I2C2 126 #define CONFIG_SYS_I2C_MXC_I2C3 127 #define CONFIG_SYS_I2C_MXC_I2C4 128 129 /* Command line configuration */ 130 #ifndef SPL_NO_ENV 131 #define CONFIG_CMD_ENV 132 #endif 133 134 /* MMC */ 135 #ifndef SPL_NO_MMC 136 #ifdef CONFIG_MMC 137 #define CONFIG_FSL_ESDHC 138 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 139 #endif 140 #endif 141 142 #ifndef SPL_NO_QBMAN 143 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 144 #endif 145 146 /* FMan ucode */ 147 #ifndef SPL_NO_FMAN 148 #define CONFIG_SYS_DPAA_FMAN 149 #ifdef CONFIG_SYS_DPAA_FMAN 150 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 151 #endif 152 153 #ifdef CONFIG_SD_BOOT 154 /* 155 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 156 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 157 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 158 */ 159 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 160 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 161 #elif defined(CONFIG_QSPI_BOOT) 162 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 163 #define CONFIG_SYS_FMAN_FW_ADDR 0x40300000 164 #define CONFIG_ENV_SPI_BUS 0 165 #define CONFIG_ENV_SPI_CS 0 166 #define CONFIG_ENV_SPI_MAX_HZ 1000000 167 #define CONFIG_ENV_SPI_MODE 0x03 168 #elif defined(CONFIG_NAND_BOOT) 169 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 170 #define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 171 #else 172 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 173 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 174 #endif 175 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 176 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 177 #endif 178 179 /* Miscellaneous configurable options */ 180 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 181 182 #define CONFIG_HWCONFIG 183 #define HWCONFIG_BUFFER_SIZE 128 184 185 #ifndef SPL_NO_MISC 186 /* Initial environment variables */ 187 #define CONFIG_EXTRA_ENV_SETTINGS \ 188 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 189 "loadaddr=0x80100000\0" \ 190 "ramdisk_addr=0x800000\0" \ 191 "ramdisk_size=0x2000000\0" \ 192 "fdt_high=0xffffffffffffffff\0" \ 193 "initrd_high=0xffffffffffffffff\0" \ 194 "kernel_start=0x1000000\0" \ 195 "kernel_load=0xa0000000\0" \ 196 "kernel_size=0x2800000\0" \ 197 "console=ttyS0,115200\0" \ 198 MTDPARTS_DEFAULT "\0" 199 200 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 201 "earlycon=uart8250,mmio,0x21c0500 " \ 202 MTDPARTS_DEFAULT 203 #endif 204 205 /* Monitor Command Prompt */ 206 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 207 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 208 sizeof(CONFIG_SYS_PROMPT) + 16) 209 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 210 #define CONFIG_SYS_LONGHELP 211 212 #ifndef SPL_NO_MISC 213 #define CONFIG_CMDLINE_EDITING 1 214 #endif 215 216 #define CONFIG_AUTO_COMPLETE 217 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 218 219 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 220 221 /* Hash command with SHA acceleration supported in hardware */ 222 #ifdef CONFIG_FSL_CAAM 223 #define CONFIG_CMD_HASH 224 #define CONFIG_SHA_HW_ACCEL 225 #endif 226 227 #endif /* __LS1046A_COMMON_H */ 228