1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043ARDB_H__ 8 #define __LS1043ARDB_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #else 15 #define CONFIG_SYS_TEXT_BASE 0x60100000 16 #endif 17 18 #define CONFIG_SYS_CLK_FREQ 100000000 19 #define CONFIG_DDR_CLK_FREQ 100000000 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 #define CONFIG_MISC_INIT_R 23 24 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 25 /* Physical Memory Map */ 26 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 27 #define CONFIG_NR_DRAM_BANKS 2 28 29 #define CONFIG_SYS_SPD_BUS_NUM 0 30 31 #define CONFIG_FSL_DDR_BIST 32 #ifndef CONFIG_SPL 33 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 34 #endif 35 #define CONFIG_SYS_DDR_RAW_TIMING 36 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 37 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 38 39 #ifdef CONFIG_RAMBOOT_PBL 40 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 41 #endif 42 43 #ifdef CONFIG_NAND_BOOT 44 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 45 #endif 46 47 #ifdef CONFIG_SD_BOOT 48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 49 #endif 50 51 /* 52 * NOR Flash Definitions 53 */ 54 #define CONFIG_SYS_NOR_CSPR_EXT (0x0) 55 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 56 #define CONFIG_SYS_NOR_CSPR \ 57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 58 CSPR_PORT_SIZE_16 | \ 59 CSPR_MSEL_NOR | \ 60 CSPR_V) 61 62 /* NOR Flash Timing Params */ 63 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 64 CSOR_NOR_TRHZ_80) 65 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 66 FTIM0_NOR_TEADC(0x1) | \ 67 FTIM0_NOR_TAVDS(0x0) | \ 68 FTIM0_NOR_TEAHC(0xc)) 69 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 70 FTIM1_NOR_TRAD_NOR(0xb) | \ 71 FTIM1_NOR_TSEQRAD_NOR(0x9)) 72 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 73 FTIM2_NOR_TCH(0x4) | \ 74 FTIM2_NOR_TWPH(0x8) | \ 75 FTIM2_NOR_TWP(0x10)) 76 #define CONFIG_SYS_NOR_FTIM3 0 77 #define CONFIG_SYS_IFC_CCR 0x01000000 78 79 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 80 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 81 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 82 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 83 84 #define CONFIG_SYS_FLASH_EMPTY_INFO 85 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 86 87 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 88 #define CONFIG_SYS_WRITE_SWAPPED_DATA 89 90 /* 91 * NAND Flash Definitions 92 */ 93 #ifndef SPL_NO_IFC 94 #define CONFIG_NAND_FSL_IFC 95 #endif 96 97 #define CONFIG_SYS_NAND_BASE 0x7e800000 98 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 99 100 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 101 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 102 | CSPR_PORT_SIZE_8 \ 103 | CSPR_MSEL_NAND \ 104 | CSPR_V) 105 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 106 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 107 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 108 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 109 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 110 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 111 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 112 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 113 114 #define CONFIG_SYS_NAND_ONFI_DETECTION 115 116 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 117 FTIM0_NAND_TWP(0x18) | \ 118 FTIM0_NAND_TWCHT(0x7) | \ 119 FTIM0_NAND_TWH(0xa)) 120 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 121 FTIM1_NAND_TWBE(0x39) | \ 122 FTIM1_NAND_TRR(0xe) | \ 123 FTIM1_NAND_TRP(0x18)) 124 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 125 FTIM2_NAND_TREH(0xa) | \ 126 FTIM2_NAND_TWHRE(0x1e)) 127 #define CONFIG_SYS_NAND_FTIM3 0x0 128 129 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 131 #define CONFIG_MTD_NAND_VERIFY_WRITE 132 133 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 134 135 #ifdef CONFIG_NAND_BOOT 136 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 137 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 138 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) 139 #endif 140 141 /* 142 * CPLD 143 */ 144 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 145 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 146 147 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 148 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 149 CSPR_PORT_SIZE_8 | \ 150 CSPR_MSEL_GPCM | \ 151 CSPR_V) 152 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 153 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 154 CSOR_NOR_NOR_MODE_AVD_NOR | \ 155 CSOR_NOR_TRHZ_80) 156 157 /* CPLD Timing parameters for IFC GPCM */ 158 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 159 FTIM0_GPCM_TEADC(0xf) | \ 160 FTIM0_GPCM_TEAHC(0xf)) 161 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 162 FTIM1_GPCM_TRAD(0x3f)) 163 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 164 FTIM2_GPCM_TCH(0xf) | \ 165 FTIM2_GPCM_TWP(0xff)) 166 #define CONFIG_SYS_CPLD_FTIM3 0x0 167 168 /* IFC Timing Params */ 169 #ifdef CONFIG_NAND_BOOT 170 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 171 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 172 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 173 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 174 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 175 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 176 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 177 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 178 179 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 180 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 181 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 182 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 183 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 184 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 185 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 186 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 187 #else 188 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 189 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 190 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 191 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 192 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 193 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 194 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 195 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 196 197 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 198 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 199 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 200 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 201 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 202 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 203 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 204 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 205 #endif 206 207 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 208 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 209 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 215 216 /* EEPROM */ 217 #ifndef SPL_NO_EEPROM 218 #define CONFIG_ID_EEPROM 219 #define CONFIG_SYS_I2C_EEPROM_NXID 220 #define CONFIG_SYS_EEPROM_BUS_NUM 0 221 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 225 #endif 226 227 /* 228 * Environment 229 */ 230 #ifndef SPL_NO_ENV 231 #define CONFIG_ENV_OVERWRITE 232 #endif 233 234 #if defined(CONFIG_NAND_BOOT) 235 #define CONFIG_ENV_SIZE 0x2000 236 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 237 #elif defined(CONFIG_SD_BOOT) 238 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 239 #define CONFIG_SYS_MMC_ENV_DEV 0 240 #define CONFIG_ENV_SIZE 0x2000 241 #else 242 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 243 #define CONFIG_ENV_SECT_SIZE 0x20000 244 #define CONFIG_ENV_SIZE 0x20000 245 #endif 246 247 /* FMan */ 248 #ifndef SPL_NO_FMAN 249 #define AQR105_IRQ_MASK 0x40000000 250 251 #ifdef CONFIG_NET 252 #define CONFIG_PHY_VITESSE 253 #define CONFIG_PHY_REALTEK 254 #endif 255 256 #ifdef CONFIG_SYS_DPAA_FMAN 257 #define CONFIG_FMAN_ENET 258 #define CONFIG_PHYLIB_10G 259 #define CONFIG_PHY_AQUANTIA 260 261 #define RGMII_PHY1_ADDR 0x1 262 #define RGMII_PHY2_ADDR 0x2 263 264 #define QSGMII_PORT1_PHY_ADDR 0x4 265 #define QSGMII_PORT2_PHY_ADDR 0x5 266 #define QSGMII_PORT3_PHY_ADDR 0x6 267 #define QSGMII_PORT4_PHY_ADDR 0x7 268 269 #define FM1_10GEC1_PHY_ADDR 0x1 270 271 #define CONFIG_ETHPRIME "FM1@DTSEC3" 272 #endif 273 #endif 274 275 /* QE */ 276 #ifndef SPL_NO_QE 277 #if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT) 278 #define CONFIG_U_QE 279 #endif 280 #endif 281 282 /* USB */ 283 #ifndef SPL_NO_USB 284 #define CONFIG_HAS_FSL_XHCI_USB 285 #ifdef CONFIG_HAS_FSL_XHCI_USB 286 #define CONFIG_USB_XHCI_FSL 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 288 #endif 289 #endif 290 291 /* SATA */ 292 #ifndef SPL_NO_SATA 293 #define CONFIG_LIBATA 294 #define CONFIG_SCSI_AHCI 295 #ifndef CONFIG_CMD_EXT2 296 #define CONFIG_CMD_EXT2 297 #endif 298 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 299 #define CONFIG_SYS_SCSI_MAX_LUN 2 300 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 301 CONFIG_SYS_SCSI_MAX_LUN) 302 #define SCSI_VEND_ID 0x1b4b 303 #define SCSI_DEV_ID 0x9170 304 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 305 #endif 306 307 #include <asm/fsl_secure_boot.h> 308 309 #endif /* __LS1043ARDB_H__ */ 310