1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1043ARDB_H__ 7 #define __LS1043ARDB_H__ 8 9 #include "ls1043a_common.h" 10 11 #define CONFIG_SYS_CLK_FREQ 100000000 12 #define CONFIG_DDR_CLK_FREQ 100000000 13 14 #define CONFIG_LAYERSCAPE_NS_ACCESS 15 #define CONFIG_MISC_INIT_R 16 17 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 18 /* Physical Memory Map */ 19 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 20 #define CONFIG_NR_DRAM_BANKS 2 21 22 #define CONFIG_SYS_SPD_BUS_NUM 0 23 24 #ifndef CONFIG_SPL 25 #define CONFIG_SYS_DDR_RAW_TIMING 26 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 27 #define CONFIG_FSL_DDR_BIST 28 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 29 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 30 #endif 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 34 #endif 35 36 #ifdef CONFIG_NAND_BOOT 37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 38 #endif 39 40 #ifdef CONFIG_SD_BOOT 41 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 42 #define CONFIG_CMD_SPL 43 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 44 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 45 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 46 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 47 #endif 48 49 /* 50 * NOR Flash Definitions 51 */ 52 #define CONFIG_SYS_NOR_CSPR_EXT (0x0) 53 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 54 #define CONFIG_SYS_NOR_CSPR \ 55 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 56 CSPR_PORT_SIZE_16 | \ 57 CSPR_MSEL_NOR | \ 58 CSPR_V) 59 60 /* NOR Flash Timing Params */ 61 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 62 CSOR_NOR_TRHZ_80) 63 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 64 FTIM0_NOR_TEADC(0x1) | \ 65 FTIM0_NOR_TAVDS(0x0) | \ 66 FTIM0_NOR_TEAHC(0xc)) 67 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 68 FTIM1_NOR_TRAD_NOR(0xb) | \ 69 FTIM1_NOR_TSEQRAD_NOR(0x9)) 70 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 71 FTIM2_NOR_TCH(0x4) | \ 72 FTIM2_NOR_TWPH(0x8) | \ 73 FTIM2_NOR_TWP(0x10)) 74 #define CONFIG_SYS_NOR_FTIM3 0 75 #define CONFIG_SYS_IFC_CCR 0x01000000 76 77 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 78 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 79 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 80 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 81 82 #define CONFIG_SYS_FLASH_EMPTY_INFO 83 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 84 85 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 86 #define CONFIG_SYS_WRITE_SWAPPED_DATA 87 88 /* 89 * NAND Flash Definitions 90 */ 91 #ifndef SPL_NO_IFC 92 #define CONFIG_NAND_FSL_IFC 93 #endif 94 95 #define CONFIG_SYS_NAND_BASE 0x7e800000 96 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 97 98 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 99 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 100 | CSPR_PORT_SIZE_8 \ 101 | CSPR_MSEL_NAND \ 102 | CSPR_V) 103 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 104 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 106 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 107 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 108 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 109 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 110 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 111 112 #define CONFIG_SYS_NAND_ONFI_DETECTION 113 114 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 115 FTIM0_NAND_TWP(0x18) | \ 116 FTIM0_NAND_TWCHT(0x7) | \ 117 FTIM0_NAND_TWH(0xa)) 118 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 119 FTIM1_NAND_TWBE(0x39) | \ 120 FTIM1_NAND_TRR(0xe) | \ 121 FTIM1_NAND_TRP(0x18)) 122 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 123 FTIM2_NAND_TREH(0xa) | \ 124 FTIM2_NAND_TWHRE(0x1e)) 125 #define CONFIG_SYS_NAND_FTIM3 0x0 126 127 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 128 #define CONFIG_SYS_MAX_NAND_DEVICE 1 129 #define CONFIG_MTD_NAND_VERIFY_WRITE 130 131 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 132 133 #ifdef CONFIG_NAND_BOOT 134 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 135 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 136 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) 137 #endif 138 139 /* 140 * CPLD 141 */ 142 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 143 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 144 145 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 146 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 147 CSPR_PORT_SIZE_8 | \ 148 CSPR_MSEL_GPCM | \ 149 CSPR_V) 150 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 151 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 152 CSOR_NOR_NOR_MODE_AVD_NOR | \ 153 CSOR_NOR_TRHZ_80) 154 155 /* CPLD Timing parameters for IFC GPCM */ 156 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 157 FTIM0_GPCM_TEADC(0xf) | \ 158 FTIM0_GPCM_TEAHC(0xf)) 159 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 160 FTIM1_GPCM_TRAD(0x3f)) 161 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 162 FTIM2_GPCM_TCH(0xf) | \ 163 FTIM2_GPCM_TWP(0xff)) 164 #define CONFIG_SYS_CPLD_FTIM3 0x0 165 166 /* IFC Timing Params */ 167 #ifdef CONFIG_NAND_BOOT 168 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 169 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 170 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 171 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 172 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 173 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 174 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 175 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 176 177 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 178 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 179 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 180 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 181 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 182 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 183 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 184 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 185 #else 186 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 187 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 188 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 189 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 190 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 191 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 192 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 193 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 194 195 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 196 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 198 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 199 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 200 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 201 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 202 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 203 #endif 204 205 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 206 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 207 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 208 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 209 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 210 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 211 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 212 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 213 214 /* EEPROM */ 215 #ifndef SPL_NO_EEPROM 216 #define CONFIG_ID_EEPROM 217 #define CONFIG_SYS_I2C_EEPROM_NXID 218 #define CONFIG_SYS_EEPROM_BUS_NUM 0 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 223 #endif 224 225 /* 226 * Environment 227 */ 228 #ifndef SPL_NO_ENV 229 #define CONFIG_ENV_OVERWRITE 230 #endif 231 232 #if defined(CONFIG_NAND_BOOT) 233 #define CONFIG_ENV_SIZE 0x2000 234 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 235 #elif defined(CONFIG_SD_BOOT) 236 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 237 #define CONFIG_SYS_MMC_ENV_DEV 0 238 #define CONFIG_ENV_SIZE 0x2000 239 #else 240 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 241 #define CONFIG_ENV_SECT_SIZE 0x20000 242 #define CONFIG_ENV_SIZE 0x20000 243 #endif 244 245 /* FMan */ 246 #ifndef SPL_NO_FMAN 247 #define AQR105_IRQ_MASK 0x40000000 248 249 #ifdef CONFIG_NET 250 #define CONFIG_PHY_VITESSE 251 #define CONFIG_PHY_REALTEK 252 #endif 253 254 #ifdef CONFIG_SYS_DPAA_FMAN 255 #define CONFIG_FMAN_ENET 256 #define CONFIG_PHYLIB_10G 257 #define CONFIG_PHY_AQUANTIA 258 259 #define RGMII_PHY1_ADDR 0x1 260 #define RGMII_PHY2_ADDR 0x2 261 262 #define QSGMII_PORT1_PHY_ADDR 0x4 263 #define QSGMII_PORT2_PHY_ADDR 0x5 264 #define QSGMII_PORT3_PHY_ADDR 0x6 265 #define QSGMII_PORT4_PHY_ADDR 0x7 266 267 #define FM1_10GEC1_PHY_ADDR 0x1 268 269 #define CONFIG_ETHPRIME "FM1@DTSEC3" 270 #endif 271 #endif 272 273 /* QE */ 274 #ifndef SPL_NO_QE 275 #if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT) 276 #define CONFIG_U_QE 277 #endif 278 #endif 279 280 /* SATA */ 281 #ifndef SPL_NO_SATA 282 #ifndef CONFIG_CMD_EXT2 283 #define CONFIG_CMD_EXT2 284 #endif 285 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 286 #define CONFIG_SYS_SCSI_MAX_LUN 2 287 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 288 CONFIG_SYS_SCSI_MAX_LUN) 289 #define SCSI_VEND_ID 0x1b4b 290 #define SCSI_DEV_ID 0x9170 291 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 292 #endif 293 294 #include <asm/fsl_secure_boot.h> 295 296 #endif /* __LS1043ARDB_H__ */ 297