1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043ARDB_H__ 8 #define __LS1043ARDB_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_FSL_LS_PPA) 13 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT 14 #define SEC_FIRMWARE_ERET_ADDR_REVERT 15 #define CONFIG_ARMV8_PSCI 16 17 #define CONFIG_SYS_LS_PPA_FW_IN_XIP 18 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP 19 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 20 #endif 21 #endif 22 23 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 24 #define CONFIG_SYS_TEXT_BASE 0x82000000 25 #else 26 #define CONFIG_SYS_TEXT_BASE 0x60100000 27 #endif 28 29 #define CONFIG_SYS_CLK_FREQ 100000000 30 #define CONFIG_DDR_CLK_FREQ 100000000 31 32 #define CONFIG_LAYERSCAPE_NS_ACCESS 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 36 /* Physical Memory Map */ 37 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 38 #define CONFIG_NR_DRAM_BANKS 2 39 40 #define CONFIG_SYS_SPD_BUS_NUM 0 41 42 #define CONFIG_FSL_DDR_BIST 43 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 44 #define CONFIG_SYS_DDR_RAW_TIMING 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 50 #endif 51 52 #ifdef CONFIG_NAND_BOOT 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 54 #endif 55 56 #ifdef CONFIG_SD_BOOT 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 58 #endif 59 60 /* 61 * NOR Flash Definitions 62 */ 63 #define CONFIG_SYS_NOR_CSPR_EXT (0x0) 64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 65 #define CONFIG_SYS_NOR_CSPR \ 66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 67 CSPR_PORT_SIZE_16 | \ 68 CSPR_MSEL_NOR | \ 69 CSPR_V) 70 71 /* NOR Flash Timing Params */ 72 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 73 CSOR_NOR_TRHZ_80) 74 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 75 FTIM0_NOR_TEADC(0x1) | \ 76 FTIM0_NOR_TAVDS(0x0) | \ 77 FTIM0_NOR_TEAHC(0xc)) 78 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 79 FTIM1_NOR_TRAD_NOR(0xb) | \ 80 FTIM1_NOR_TSEQRAD_NOR(0x9)) 81 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 82 FTIM2_NOR_TCH(0x4) | \ 83 FTIM2_NOR_TWPH(0x8) | \ 84 FTIM2_NOR_TWP(0x10)) 85 #define CONFIG_SYS_NOR_FTIM3 0 86 #define CONFIG_SYS_IFC_CCR 0x01000000 87 88 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 89 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 90 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 91 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 92 93 #define CONFIG_SYS_FLASH_EMPTY_INFO 94 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 95 96 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 97 #define CONFIG_SYS_WRITE_SWAPPED_DATA 98 99 /* 100 * NAND Flash Definitions 101 */ 102 #define CONFIG_NAND_FSL_IFC 103 104 #define CONFIG_SYS_NAND_BASE 0x7e800000 105 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 106 107 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 108 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 109 | CSPR_PORT_SIZE_8 \ 110 | CSPR_MSEL_NAND \ 111 | CSPR_V) 112 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 113 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 114 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 115 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 116 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 117 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 118 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 119 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 120 121 #define CONFIG_SYS_NAND_ONFI_DETECTION 122 123 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 124 FTIM0_NAND_TWP(0x18) | \ 125 FTIM0_NAND_TWCHT(0x7) | \ 126 FTIM0_NAND_TWH(0xa)) 127 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 128 FTIM1_NAND_TWBE(0x39) | \ 129 FTIM1_NAND_TRR(0xe) | \ 130 FTIM1_NAND_TRP(0x18)) 131 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 132 FTIM2_NAND_TREH(0xa) | \ 133 FTIM2_NAND_TWHRE(0x1e)) 134 #define CONFIG_SYS_NAND_FTIM3 0x0 135 136 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 138 #define CONFIG_MTD_NAND_VERIFY_WRITE 139 #define CONFIG_CMD_NAND 140 141 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 142 143 #ifdef CONFIG_NAND_BOOT 144 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 145 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 146 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 147 #endif 148 149 /* 150 * CPLD 151 */ 152 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 153 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 154 155 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 156 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 157 CSPR_PORT_SIZE_8 | \ 158 CSPR_MSEL_GPCM | \ 159 CSPR_V) 160 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 161 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 162 CSOR_NOR_NOR_MODE_AVD_NOR | \ 163 CSOR_NOR_TRHZ_80) 164 165 /* CPLD Timing parameters for IFC GPCM */ 166 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 167 FTIM0_GPCM_TEADC(0xf) | \ 168 FTIM0_GPCM_TEAHC(0xf)) 169 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 170 FTIM1_GPCM_TRAD(0x3f)) 171 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 172 FTIM2_GPCM_TCH(0xf) | \ 173 FTIM2_GPCM_TWP(0xff)) 174 #define CONFIG_SYS_CPLD_FTIM3 0x0 175 176 /* IFC Timing Params */ 177 #ifdef CONFIG_NAND_BOOT 178 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 179 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 180 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 181 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 182 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 183 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 184 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 185 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 186 187 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 188 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 189 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 190 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 191 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 192 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 193 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 194 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 195 #else 196 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 197 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 204 205 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 206 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 207 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 208 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 209 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 210 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 211 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 212 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 213 #endif 214 215 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 216 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 217 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 218 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 219 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 220 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 221 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 222 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 223 224 /* EEPROM */ 225 #define CONFIG_ID_EEPROM 226 #define CONFIG_SYS_I2C_EEPROM_NXID 227 #define CONFIG_SYS_EEPROM_BUS_NUM 0 228 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 232 233 /* 234 * Environment 235 */ 236 #define CONFIG_ENV_OVERWRITE 237 238 #if defined(CONFIG_NAND_BOOT) 239 #define CONFIG_ENV_IS_IN_NAND 240 #define CONFIG_ENV_SIZE 0x2000 241 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 242 #elif defined(CONFIG_SD_BOOT) 243 #define CONFIG_ENV_OFFSET (1024 * 1024) 244 #define CONFIG_ENV_IS_IN_MMC 245 #define CONFIG_SYS_MMC_ENV_DEV 0 246 #define CONFIG_ENV_SIZE 0x2000 247 #else 248 #define CONFIG_ENV_IS_IN_FLASH 249 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 250 #define CONFIG_ENV_SECT_SIZE 0x20000 251 #define CONFIG_ENV_SIZE 0x20000 252 #endif 253 254 /* FMan */ 255 #ifdef CONFIG_SYS_DPAA_FMAN 256 #define CONFIG_FMAN_ENET 257 #define CONFIG_PHYLIB 258 #define CONFIG_PHYLIB_10G 259 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 260 261 #define CONFIG_PHY_VITESSE 262 #define CONFIG_PHY_REALTEK 263 #define CONFIG_PHY_AQUANTIA 264 #define AQR105_IRQ_MASK 0x40000000 265 266 #define RGMII_PHY1_ADDR 0x1 267 #define RGMII_PHY2_ADDR 0x2 268 269 #define QSGMII_PORT1_PHY_ADDR 0x4 270 #define QSGMII_PORT2_PHY_ADDR 0x5 271 #define QSGMII_PORT3_PHY_ADDR 0x6 272 #define QSGMII_PORT4_PHY_ADDR 0x7 273 274 #define FM1_10GEC1_PHY_ADDR 0x1 275 276 #define CONFIG_ETHPRIME "FM1@DTSEC3" 277 #endif 278 279 /* QE */ 280 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 281 !defined(CONFIG_QSPI_BOOT) 282 #define CONFIG_U_QE 283 #endif 284 #define CONFIG_SYS_QE_FW_ADDR 0x60600000 285 286 /* USB */ 287 #define CONFIG_HAS_FSL_XHCI_USB 288 #ifdef CONFIG_HAS_FSL_XHCI_USB 289 #define CONFIG_USB_XHCI_FSL 290 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 291 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 292 #endif 293 294 /* SATA */ 295 #define CONFIG_LIBATA 296 #define CONFIG_SCSI_AHCI 297 #define CONFIG_CMD_SCSI 298 #ifndef CONFIG_CMD_FAT 299 #define CONFIG_CMD_FAT 300 #endif 301 #ifndef CONFIG_CMD_EXT2 302 #define CONFIG_CMD_EXT2 303 #endif 304 #define CONFIG_DOS_PARTITION 305 #define CONFIG_BOARD_LATE_INIT 306 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 307 #define CONFIG_SYS_SCSI_MAX_LUN 2 308 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 309 CONFIG_SYS_SCSI_MAX_LUN) 310 #define SCSI_VEND_ID 0x1b4b 311 #define SCSI_DEV_ID 0x9170 312 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 313 314 #include <asm/fsl_secure_boot.h> 315 316 #endif /* __LS1043ARDB_H__ */ 317