1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043ARDB_H__ 8 #define __LS1043ARDB_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_FSL_LS_PPA) 13 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT 14 #define SEC_FIRMWARE_ERET_ADDR_REVERT 15 16 #define CONFIG_SYS_LS_PPA_FW_IN_XIP 17 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP 18 #define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 19 #endif 20 #endif 21 22 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 23 #define CONFIG_SYS_TEXT_BASE 0x82000000 24 #else 25 #define CONFIG_SYS_TEXT_BASE 0x60100000 26 #endif 27 28 #define CONFIG_SYS_CLK_FREQ 100000000 29 #define CONFIG_DDR_CLK_FREQ 100000000 30 31 #define CONFIG_LAYERSCAPE_NS_ACCESS 32 #define CONFIG_MISC_INIT_R 33 34 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 35 /* Physical Memory Map */ 36 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 37 #define CONFIG_NR_DRAM_BANKS 2 38 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #define CONFIG_FSL_DDR_BIST 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #define CONFIG_SYS_DDR_RAW_TIMING 44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 45 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 46 47 #ifdef CONFIG_RAMBOOT_PBL 48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 49 #endif 50 51 #ifdef CONFIG_NAND_BOOT 52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 53 #endif 54 55 #ifdef CONFIG_SD_BOOT 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 57 #endif 58 59 /* 60 * NOR Flash Definitions 61 */ 62 #define CONFIG_SYS_NOR_CSPR_EXT (0x0) 63 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 64 #define CONFIG_SYS_NOR_CSPR \ 65 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 66 CSPR_PORT_SIZE_16 | \ 67 CSPR_MSEL_NOR | \ 68 CSPR_V) 69 70 /* NOR Flash Timing Params */ 71 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 72 CSOR_NOR_TRHZ_80) 73 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 74 FTIM0_NOR_TEADC(0x1) | \ 75 FTIM0_NOR_TAVDS(0x0) | \ 76 FTIM0_NOR_TEAHC(0xc)) 77 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 78 FTIM1_NOR_TRAD_NOR(0xb) | \ 79 FTIM1_NOR_TSEQRAD_NOR(0x9)) 80 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 81 FTIM2_NOR_TCH(0x4) | \ 82 FTIM2_NOR_TWPH(0x8) | \ 83 FTIM2_NOR_TWP(0x10)) 84 #define CONFIG_SYS_NOR_FTIM3 0 85 #define CONFIG_SYS_IFC_CCR 0x01000000 86 87 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 88 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 91 92 #define CONFIG_SYS_FLASH_EMPTY_INFO 93 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 94 95 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 96 #define CONFIG_SYS_WRITE_SWAPPED_DATA 97 98 /* 99 * NAND Flash Definitions 100 */ 101 #define CONFIG_NAND_FSL_IFC 102 103 #define CONFIG_SYS_NAND_BASE 0x7e800000 104 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 105 106 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 107 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 108 | CSPR_PORT_SIZE_8 \ 109 | CSPR_MSEL_NAND \ 110 | CSPR_V) 111 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 112 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 113 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 114 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 115 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 116 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 117 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 118 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 119 120 #define CONFIG_SYS_NAND_ONFI_DETECTION 121 122 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 123 FTIM0_NAND_TWP(0x18) | \ 124 FTIM0_NAND_TWCHT(0x7) | \ 125 FTIM0_NAND_TWH(0xa)) 126 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 127 FTIM1_NAND_TWBE(0x39) | \ 128 FTIM1_NAND_TRR(0xe) | \ 129 FTIM1_NAND_TRP(0x18)) 130 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 131 FTIM2_NAND_TREH(0xa) | \ 132 FTIM2_NAND_TWHRE(0x1e)) 133 #define CONFIG_SYS_NAND_FTIM3 0x0 134 135 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 137 #define CONFIG_MTD_NAND_VERIFY_WRITE 138 #define CONFIG_CMD_NAND 139 140 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 141 142 #ifdef CONFIG_NAND_BOOT 143 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 144 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 145 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 146 #endif 147 148 /* 149 * CPLD 150 */ 151 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 152 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 153 154 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 155 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 156 CSPR_PORT_SIZE_8 | \ 157 CSPR_MSEL_GPCM | \ 158 CSPR_V) 159 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 160 #define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 161 CSOR_NOR_NOR_MODE_AVD_NOR | \ 162 CSOR_NOR_TRHZ_80) 163 164 /* CPLD Timing parameters for IFC GPCM */ 165 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 166 FTIM0_GPCM_TEADC(0xf) | \ 167 FTIM0_GPCM_TEAHC(0xf)) 168 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 169 FTIM1_GPCM_TRAD(0x3f)) 170 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 171 FTIM2_GPCM_TCH(0xf) | \ 172 FTIM2_GPCM_TWP(0xff)) 173 #define CONFIG_SYS_CPLD_FTIM3 0x0 174 175 /* IFC Timing Params */ 176 #ifdef CONFIG_NAND_BOOT 177 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 185 186 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 187 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 188 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 189 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 190 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 191 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 192 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 193 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 194 #else 195 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 196 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 197 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 198 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 199 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 200 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 201 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 202 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 203 204 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 205 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 206 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 207 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 208 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 209 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 210 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 211 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 212 #endif 213 214 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 215 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 216 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 217 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 218 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 219 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 220 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 221 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 222 223 /* EEPROM */ 224 #define CONFIG_ID_EEPROM 225 #define CONFIG_SYS_I2C_EEPROM_NXID 226 #define CONFIG_SYS_EEPROM_BUS_NUM 0 227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 231 232 /* 233 * Environment 234 */ 235 #define CONFIG_ENV_OVERWRITE 236 237 #if defined(CONFIG_NAND_BOOT) 238 #define CONFIG_ENV_IS_IN_NAND 239 #define CONFIG_ENV_SIZE 0x2000 240 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 241 #elif defined(CONFIG_SD_BOOT) 242 #define CONFIG_ENV_OFFSET (1024 * 1024) 243 #define CONFIG_ENV_IS_IN_MMC 244 #define CONFIG_SYS_MMC_ENV_DEV 0 245 #define CONFIG_ENV_SIZE 0x2000 246 #else 247 #define CONFIG_ENV_IS_IN_FLASH 248 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 249 #define CONFIG_ENV_SECT_SIZE 0x20000 250 #define CONFIG_ENV_SIZE 0x20000 251 #endif 252 253 /* FMan */ 254 #ifdef CONFIG_SYS_DPAA_FMAN 255 #define CONFIG_FMAN_ENET 256 #define CONFIG_PHYLIB 257 #define CONFIG_PHYLIB_10G 258 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 259 260 #define CONFIG_PHY_VITESSE 261 #define CONFIG_PHY_REALTEK 262 #define CONFIG_PHY_AQUANTIA 263 #define AQR105_IRQ_MASK 0x40000000 264 265 #define RGMII_PHY1_ADDR 0x1 266 #define RGMII_PHY2_ADDR 0x2 267 268 #define QSGMII_PORT1_PHY_ADDR 0x4 269 #define QSGMII_PORT2_PHY_ADDR 0x5 270 #define QSGMII_PORT3_PHY_ADDR 0x6 271 #define QSGMII_PORT4_PHY_ADDR 0x7 272 273 #define FM1_10GEC1_PHY_ADDR 0x1 274 275 #define CONFIG_ETHPRIME "FM1@DTSEC3" 276 #endif 277 278 /* QE */ 279 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 280 !defined(CONFIG_QSPI_BOOT) 281 #define CONFIG_U_QE 282 #endif 283 #define CONFIG_SYS_QE_FW_ADDR 0x60600000 284 285 /* USB */ 286 #define CONFIG_HAS_FSL_XHCI_USB 287 #ifdef CONFIG_HAS_FSL_XHCI_USB 288 #define CONFIG_USB_XHCI_FSL 289 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 290 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 291 #endif 292 293 /* SATA */ 294 #define CONFIG_LIBATA 295 #define CONFIG_SCSI_AHCI 296 #define CONFIG_CMD_SCSI 297 #ifndef CONFIG_CMD_FAT 298 #define CONFIG_CMD_FAT 299 #endif 300 #ifndef CONFIG_CMD_EXT2 301 #define CONFIG_CMD_EXT2 302 #endif 303 #define CONFIG_DOS_PARTITION 304 #define CONFIG_BOARD_LATE_INIT 305 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 306 #define CONFIG_SYS_SCSI_MAX_LUN 2 307 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 308 CONFIG_SYS_SCSI_MAX_LUN) 309 #define SCSI_VEND_ID 0x1b4b 310 #define SCSI_DEV_ID 0x9170 311 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 312 313 #include <asm/fsl_secure_boot.h> 314 315 #endif /* __LS1043ARDB_H__ */ 316