1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 16 #define CONFIG_SYS_TEXT_BASE 0x82000000 17 #else 18 #define CONFIG_SYS_TEXT_BASE 0x60100000 19 #endif 20 21 #ifndef __ASSEMBLY__ 22 unsigned long get_board_sys_clk(void); 23 unsigned long get_board_ddr_clk(void); 24 #endif 25 26 #define CONFIG_SYS_CLK_FREQ 100000000 27 #define CONFIG_DDR_CLK_FREQ 100000000 28 29 #define CONFIG_SKIP_LOWLEVEL_INIT 30 31 #define CONFIG_LAYERSCAPE_NS_ACCESS 32 33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 34 /* Physical Memory Map */ 35 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 36 #define CONFIG_NR_DRAM_BANKS 1 37 38 #define CONFIG_DDR_SPD 39 #define SPD_EEPROM_ADDRESS 0x51 40 #define CONFIG_SYS_SPD_BUS_NUM 0 41 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #ifndef CONFIG_SYS_FSL_DDR4 44 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 45 #endif 46 47 #define CONFIG_DDR_ECC 48 #ifdef CONFIG_DDR_ECC 49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 51 #endif 52 53 #define CONFIG_SYS_HAS_SERDES 54 55 #ifdef CONFIG_SYS_DPAA_FMAN 56 #define CONFIG_FMAN_ENET 57 #define CONFIG_PHYLIB 58 #define CONFIG_PHY_VITESSE 59 #define CONFIG_PHY_REALTEK 60 #define CONFIG_PHYLIB_10G 61 #define RGMII_PHY1_ADDR 0x1 62 #define RGMII_PHY2_ADDR 0x2 63 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 64 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 65 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 66 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 67 /* PHY address on QSGMII riser card on slot 1 */ 68 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 69 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 70 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 71 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 72 /* PHY address on QSGMII riser card on slot 2 */ 73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 77 #endif 78 79 #ifdef CONFIG_RAMBOOT_PBL 80 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 81 #endif 82 83 #ifdef CONFIG_NAND_BOOT 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 85 #endif 86 87 #ifdef CONFIG_SD_BOOT 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 89 #endif 90 91 /* SATA */ 92 #define CONFIG_LIBATA 93 #define CONFIG_SCSI_AHCI 94 #define CONFIG_SCSI_AHCI_PLAT 95 #define CONFIG_CMD_SCSI 96 #define CONFIG_CMD_FAT 97 #define CONFIG_CMD_EXT2 98 #define CONFIG_DOS_PARTITION 99 #define CONFIG_BOARD_LATE_INIT 100 101 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 102 103 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 104 #define CONFIG_SYS_SCSI_MAX_LUN 1 105 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 106 CONFIG_SYS_SCSI_MAX_LUN) 107 108 /* 109 * IFC Definitions 110 */ 111 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 112 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 113 CSPR_PORT_SIZE_16 | \ 114 CSPR_MSEL_NOR | \ 115 CSPR_V) 116 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 117 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 118 + 0x8000000) | \ 119 CSPR_PORT_SIZE_16 | \ 120 CSPR_MSEL_NOR | \ 121 CSPR_V) 122 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 123 124 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 125 CSOR_NOR_TRHZ_80) 126 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 127 FTIM0_NOR_TEADC(0x5) | \ 128 FTIM0_NOR_TEAHC(0x5)) 129 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 130 FTIM1_NOR_TRAD_NOR(0x1a) | \ 131 FTIM1_NOR_TSEQRAD_NOR(0x13)) 132 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 133 FTIM2_NOR_TCH(0x4) | \ 134 FTIM2_NOR_TWPH(0xe) | \ 135 FTIM2_NOR_TWP(0x1c)) 136 #define CONFIG_SYS_NOR_FTIM3 0 137 138 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 139 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 140 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 141 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 142 143 #define CONFIG_SYS_FLASH_EMPTY_INFO 144 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 145 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 146 147 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 148 #define CONFIG_SYS_WRITE_SWAPPED_DATA 149 150 /* 151 * NAND Flash Definitions 152 */ 153 #define CONFIG_NAND_FSL_IFC 154 155 #define CONFIG_SYS_NAND_BASE 0x7e800000 156 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 157 158 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 159 160 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 161 | CSPR_PORT_SIZE_8 \ 162 | CSPR_MSEL_NAND \ 163 | CSPR_V) 164 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 165 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 166 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 167 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 168 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 169 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 170 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 171 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 172 173 #define CONFIG_SYS_NAND_ONFI_DETECTION 174 175 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 176 FTIM0_NAND_TWP(0x18) | \ 177 FTIM0_NAND_TWCHT(0x7) | \ 178 FTIM0_NAND_TWH(0xa)) 179 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 180 FTIM1_NAND_TWBE(0x39) | \ 181 FTIM1_NAND_TRR(0xe) | \ 182 FTIM1_NAND_TRP(0x18)) 183 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 184 FTIM2_NAND_TREH(0xa) | \ 185 FTIM2_NAND_TWHRE(0x1e)) 186 #define CONFIG_SYS_NAND_FTIM3 0x0 187 188 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 189 #define CONFIG_SYS_MAX_NAND_DEVICE 1 190 #define CONFIG_MTD_NAND_VERIFY_WRITE 191 #define CONFIG_CMD_NAND 192 193 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 194 195 #ifdef CONFIG_NAND_BOOT 196 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 197 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 198 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 199 #endif 200 201 /* 202 * QIXIS Definitions 203 */ 204 #define CONFIG_FSL_QIXIS 205 206 #ifdef CONFIG_FSL_QIXIS 207 #define QIXIS_BASE 0x7fb00000 208 #define QIXIS_BASE_PHYS QIXIS_BASE 209 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 210 #define QIXIS_LBMAP_SWITCH 6 211 #define QIXIS_LBMAP_MASK 0x0f 212 #define QIXIS_LBMAP_SHIFT 0 213 #define QIXIS_LBMAP_DFLTBANK 0x00 214 #define QIXIS_LBMAP_ALTBANK 0x04 215 #define QIXIS_RST_CTL_RESET 0x44 216 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 217 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 218 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 219 220 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 221 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 222 CSPR_PORT_SIZE_8 | \ 223 CSPR_MSEL_GPCM | \ 224 CSPR_V) 225 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 226 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 227 CSOR_NOR_NOR_MODE_AVD_NOR | \ 228 CSOR_NOR_TRHZ_80) 229 230 /* 231 * QIXIS Timing parameters for IFC GPCM 232 */ 233 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 234 FTIM0_GPCM_TEADC(0x20) | \ 235 FTIM0_GPCM_TEAHC(0x10)) 236 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 237 FTIM1_GPCM_TRAD(0x1f)) 238 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 239 FTIM2_GPCM_TCH(0x8) | \ 240 FTIM2_GPCM_TWP(0xf0)) 241 #define CONFIG_SYS_FPGA_FTIM3 0x0 242 #endif 243 244 #ifdef CONFIG_NAND_BOOT 245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 247 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 248 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 249 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 250 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 251 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 252 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 253 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 254 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 255 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 256 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 257 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 258 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 259 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 260 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 261 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 262 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 263 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 264 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 265 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 266 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 267 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 268 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 269 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 270 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 271 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 272 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 273 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 274 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 275 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 276 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 277 #else 278 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 279 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 280 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 281 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 282 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 283 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 284 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 285 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 286 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 287 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 288 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 289 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 290 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 291 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 292 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 293 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 294 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 295 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 296 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 297 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 298 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 299 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 300 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 301 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 302 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 303 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 304 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 305 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 306 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 307 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 308 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 309 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 310 #endif 311 312 /* 313 * I2C bus multiplexer 314 */ 315 #define I2C_MUX_PCA_ADDR_PRI 0x77 316 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 317 #define I2C_RETIMER_ADDR 0x18 318 #define I2C_MUX_CH_DEFAULT 0x8 319 #define I2C_MUX_CH_CH7301 0xC 320 #define I2C_MUX_CH5 0xD 321 #define I2C_MUX_CH7 0xF 322 323 #define I2C_MUX_CH_VOL_MONITOR 0xa 324 325 /* Voltage monitor on channel 2*/ 326 #define I2C_VOL_MONITOR_ADDR 0x40 327 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 328 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 329 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 330 331 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 332 #ifndef CONFIG_SPL_BUILD 333 #define CONFIG_VID 334 #endif 335 #define CONFIG_VOL_MONITOR_IR36021_SET 336 #define CONFIG_VOL_MONITOR_INA220 337 /* The lowest and highest voltage allowed for LS1043AQDS */ 338 #define VDD_MV_MIN 819 339 #define VDD_MV_MAX 1212 340 341 /* 342 * Miscellaneous configurable options 343 */ 344 #define CONFIG_MISC_INIT_R 345 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 346 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 347 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 348 #define CONFIG_SYS_PROMPT "=> " 349 #define CONFIG_AUTO_COMPLETE 350 #define CONFIG_SYS_PBSIZE \ 351 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 352 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 353 354 #define CONFIG_CMD_GREPENV 355 #define CONFIG_CMD_MEMINFO 356 #define CONFIG_CMD_MEMTEST 357 #define CONFIG_SYS_MEMTEST_START 0x80000000 358 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 359 360 #define CONFIG_SYS_HZ 1000 361 362 /* 363 * Stack sizes 364 * The stack sizes are set up in start.S using the settings below 365 */ 366 #define CONFIG_STACKSIZE (30 * 1024) 367 368 #define CONFIG_SYS_INIT_SP_OFFSET \ 369 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 370 371 #ifdef CONFIG_SPL_BUILD 372 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 373 #else 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 375 #endif 376 377 /* 378 * Environment 379 */ 380 #define CONFIG_ENV_OVERWRITE 381 382 #ifdef CONFIG_NAND_BOOT 383 #define CONFIG_ENV_IS_IN_NAND 384 #define CONFIG_ENV_SIZE 0x2000 385 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 386 #elif defined(CONFIG_SD_BOOT) 387 #define CONFIG_ENV_OFFSET (1024 * 1024) 388 #define CONFIG_ENV_IS_IN_MMC 389 #define CONFIG_SYS_MMC_ENV_DEV 0 390 #define CONFIG_ENV_SIZE 0x2000 391 #else 392 #define CONFIG_ENV_IS_IN_FLASH 393 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 394 #define CONFIG_ENV_SECT_SIZE 0x20000 395 #define CONFIG_ENV_SIZE 0x20000 396 #endif 397 398 #define CONFIG_OF_LIBFDT 399 #define CONFIG_OF_BOARD_SETUP 400 #define CONFIG_CMD_BOOTZ 401 #define CONFIG_CMD_MII 402 #define CONFIG_CMDLINE_TAG 403 404 #endif /* __LS1043AQDS_H__ */ 405