1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #ifdef CONFIG_QSPI_BOOT 14 #define CONFIG_DISPLAY_BOARDINFO_LATE 15 #else 16 #define CONFIG_DISPLAY_BOARDINFO 17 #endif 18 19 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 20 #define CONFIG_SYS_TEXT_BASE 0x82000000 21 #elif defined(CONFIG_QSPI_BOOT) 22 #define CONFIG_SYS_TEXT_BASE 0x40010000 23 #else 24 #define CONFIG_SYS_TEXT_BASE 0x60100000 25 #endif 26 27 #ifndef __ASSEMBLY__ 28 unsigned long get_board_sys_clk(void); 29 unsigned long get_board_ddr_clk(void); 30 #endif 31 32 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_DDR_CLK_FREQ 100000000 34 35 #define CONFIG_SKIP_LOWLEVEL_INIT 36 37 #define CONFIG_LAYERSCAPE_NS_ACCESS 38 39 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 40 /* Physical Memory Map */ 41 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 42 #define CONFIG_NR_DRAM_BANKS 2 43 44 #define CONFIG_DDR_SPD 45 #define SPD_EEPROM_ADDRESS 0x51 46 #define CONFIG_SYS_SPD_BUS_NUM 0 47 48 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 49 #ifndef CONFIG_SYS_FSL_DDR4 50 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 51 #endif 52 53 #define CONFIG_DDR_ECC 54 #ifdef CONFIG_DDR_ECC 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 56 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 57 #endif 58 59 #define CONFIG_SYS_HAS_SERDES 60 61 #ifdef CONFIG_SYS_DPAA_FMAN 62 #define CONFIG_FMAN_ENET 63 #define CONFIG_PHYLIB 64 #define CONFIG_PHY_VITESSE 65 #define CONFIG_PHY_REALTEK 66 #define CONFIG_PHYLIB_10G 67 #define RGMII_PHY1_ADDR 0x1 68 #define RGMII_PHY2_ADDR 0x2 69 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 70 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 71 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 72 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 73 /* PHY address on QSGMII riser card on slot 1 */ 74 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 75 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 76 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 77 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 78 /* PHY address on QSGMII riser card on slot 2 */ 79 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 80 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 81 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 82 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 83 #endif 84 85 #ifdef CONFIG_RAMBOOT_PBL 86 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 87 #endif 88 89 #ifdef CONFIG_NAND_BOOT 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 91 #endif 92 93 #ifdef CONFIG_SD_BOOT 94 #ifdef CONFIG_SD_BOOT_QSPI 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 97 #else 98 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 99 #endif 100 #endif 101 102 /* LPUART */ 103 #ifdef CONFIG_LPUART 104 #define CONFIG_LPUART_32B_REG 105 #endif 106 107 /* SATA */ 108 #define CONFIG_LIBATA 109 #define CONFIG_SCSI_AHCI 110 #define CONFIG_SCSI_AHCI_PLAT 111 #define CONFIG_SCSI 112 #define CONFIG_DOS_PARTITION 113 #define CONFIG_BOARD_LATE_INIT 114 115 /* EEPROM */ 116 #define CONFIG_ID_EEPROM 117 #define CONFIG_SYS_I2C_EEPROM_NXID 118 #define CONFIG_SYS_EEPROM_BUS_NUM 0 119 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 122 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 123 124 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 125 126 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 127 #define CONFIG_SYS_SCSI_MAX_LUN 1 128 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 129 CONFIG_SYS_SCSI_MAX_LUN) 130 131 /* 132 * IFC Definitions 133 */ 134 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 135 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 136 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 137 CSPR_PORT_SIZE_16 | \ 138 CSPR_MSEL_NOR | \ 139 CSPR_V) 140 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 141 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 142 + 0x8000000) | \ 143 CSPR_PORT_SIZE_16 | \ 144 CSPR_MSEL_NOR | \ 145 CSPR_V) 146 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 147 148 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 149 CSOR_NOR_TRHZ_80) 150 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 151 FTIM0_NOR_TEADC(0x5) | \ 152 FTIM0_NOR_TEAHC(0x5)) 153 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 154 FTIM1_NOR_TRAD_NOR(0x1a) | \ 155 FTIM1_NOR_TSEQRAD_NOR(0x13)) 156 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 157 FTIM2_NOR_TCH(0x4) | \ 158 FTIM2_NOR_TWPH(0xe) | \ 159 FTIM2_NOR_TWP(0x1c)) 160 #define CONFIG_SYS_NOR_FTIM3 0 161 162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #define CONFIG_SYS_FLASH_EMPTY_INFO 168 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 169 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 170 171 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 172 #define CONFIG_SYS_WRITE_SWAPPED_DATA 173 174 /* 175 * NAND Flash Definitions 176 */ 177 #define CONFIG_NAND_FSL_IFC 178 179 #define CONFIG_SYS_NAND_BASE 0x7e800000 180 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 181 182 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 183 184 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 185 | CSPR_PORT_SIZE_8 \ 186 | CSPR_MSEL_NAND \ 187 | CSPR_V) 188 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 189 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 190 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 191 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 192 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 193 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 194 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 195 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 196 197 #define CONFIG_SYS_NAND_ONFI_DETECTION 198 199 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 200 FTIM0_NAND_TWP(0x18) | \ 201 FTIM0_NAND_TWCHT(0x7) | \ 202 FTIM0_NAND_TWH(0xa)) 203 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 204 FTIM1_NAND_TWBE(0x39) | \ 205 FTIM1_NAND_TRR(0xe) | \ 206 FTIM1_NAND_TRP(0x18)) 207 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 208 FTIM2_NAND_TREH(0xa) | \ 209 FTIM2_NAND_TWHRE(0x1e)) 210 #define CONFIG_SYS_NAND_FTIM3 0x0 211 212 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 213 #define CONFIG_SYS_MAX_NAND_DEVICE 1 214 #define CONFIG_MTD_NAND_VERIFY_WRITE 215 #define CONFIG_CMD_NAND 216 217 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 218 #endif 219 220 #ifdef CONFIG_NAND_BOOT 221 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 222 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 223 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 224 #endif 225 226 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 227 #define CONFIG_QIXIS_I2C_ACCESS 228 #define CONFIG_SYS_NO_FLASH 229 #endif 230 231 /* 232 * QIXIS Definitions 233 */ 234 #define CONFIG_FSL_QIXIS 235 236 #ifdef CONFIG_FSL_QIXIS 237 #define QIXIS_BASE 0x7fb00000 238 #define QIXIS_BASE_PHYS QIXIS_BASE 239 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 240 #define QIXIS_LBMAP_SWITCH 6 241 #define QIXIS_LBMAP_MASK 0x0f 242 #define QIXIS_LBMAP_SHIFT 0 243 #define QIXIS_LBMAP_DFLTBANK 0x00 244 #define QIXIS_LBMAP_ALTBANK 0x04 245 #define QIXIS_LBMAP_NAND 0x09 246 #define QIXIS_LBMAP_SD 0x00 247 #define QIXIS_LBMAP_SD_QSPI 0xff 248 #define QIXIS_LBMAP_QSPI 0xff 249 #define QIXIS_RCW_SRC_NAND 0x106 250 #define QIXIS_RCW_SRC_SD 0x040 251 #define QIXIS_RCW_SRC_QSPI 0x045 252 #define QIXIS_RST_CTL_RESET 0x41 253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 254 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 256 257 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 258 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 259 CSPR_PORT_SIZE_8 | \ 260 CSPR_MSEL_GPCM | \ 261 CSPR_V) 262 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 263 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 264 CSOR_NOR_NOR_MODE_AVD_NOR | \ 265 CSOR_NOR_TRHZ_80) 266 267 /* 268 * QIXIS Timing parameters for IFC GPCM 269 */ 270 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 271 FTIM0_GPCM_TEADC(0x20) | \ 272 FTIM0_GPCM_TEAHC(0x10)) 273 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 274 FTIM1_GPCM_TRAD(0x1f)) 275 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 276 FTIM2_GPCM_TCH(0x8) | \ 277 FTIM2_GPCM_TWP(0xf0)) 278 #define CONFIG_SYS_FPGA_FTIM3 0x0 279 #endif 280 281 #ifdef CONFIG_NAND_BOOT 282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 299 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 300 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 307 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 308 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 309 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 310 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 311 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 312 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 313 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 314 #else 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 332 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 333 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 334 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 335 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 336 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 337 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 338 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 339 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 340 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 341 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 342 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 343 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 344 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 345 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 346 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 347 #endif 348 349 /* 350 * I2C bus multiplexer 351 */ 352 #define I2C_MUX_PCA_ADDR_PRI 0x77 353 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 354 #define I2C_RETIMER_ADDR 0x18 355 #define I2C_MUX_CH_DEFAULT 0x8 356 #define I2C_MUX_CH_CH7301 0xC 357 #define I2C_MUX_CH5 0xD 358 #define I2C_MUX_CH7 0xF 359 360 #define I2C_MUX_CH_VOL_MONITOR 0xa 361 362 /* Voltage monitor on channel 2*/ 363 #define I2C_VOL_MONITOR_ADDR 0x40 364 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 365 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 366 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 367 368 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 369 #ifndef CONFIG_SPL_BUILD 370 #define CONFIG_VID 371 #endif 372 #define CONFIG_VOL_MONITOR_IR36021_SET 373 #define CONFIG_VOL_MONITOR_INA220 374 /* The lowest and highest voltage allowed for LS1043AQDS */ 375 #define VDD_MV_MIN 819 376 #define VDD_MV_MAX 1212 377 378 /* QSPI device */ 379 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 380 #define CONFIG_FSL_QSPI 381 #ifdef CONFIG_FSL_QSPI 382 #define CONFIG_SPI_FLASH_SPANSION 383 #define FSL_QSPI_FLASH_SIZE (1 << 24) 384 #define FSL_QSPI_FLASH_NUM 2 385 #endif 386 #endif 387 388 /* USB */ 389 #define CONFIG_HAS_FSL_XHCI_USB 390 #ifdef CONFIG_HAS_FSL_XHCI_USB 391 #define CONFIG_USB_XHCI 392 #define CONFIG_USB_XHCI_FSL 393 #define CONFIG_USB_XHCI_DWC3 394 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 395 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 396 #define CONFIG_USB_STORAGE 397 #endif 398 399 /* 400 * Miscellaneous configurable options 401 */ 402 #define CONFIG_MISC_INIT_R 403 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 404 #define CONFIG_AUTO_COMPLETE 405 #define CONFIG_SYS_PBSIZE \ 406 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 407 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 408 409 #define CONFIG_SYS_MEMTEST_START 0x80000000 410 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 411 412 #define CONFIG_SYS_HZ 1000 413 414 /* 415 * Stack sizes 416 * The stack sizes are set up in start.S using the settings below 417 */ 418 #define CONFIG_STACKSIZE (30 * 1024) 419 420 #define CONFIG_SYS_INIT_SP_OFFSET \ 421 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 422 423 #ifdef CONFIG_SPL_BUILD 424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 425 #else 426 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 427 #endif 428 429 /* 430 * Environment 431 */ 432 #define CONFIG_ENV_OVERWRITE 433 434 #ifdef CONFIG_NAND_BOOT 435 #define CONFIG_ENV_IS_IN_NAND 436 #define CONFIG_ENV_SIZE 0x2000 437 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 438 #elif defined(CONFIG_SD_BOOT) 439 #define CONFIG_ENV_OFFSET (1024 * 1024) 440 #define CONFIG_ENV_IS_IN_MMC 441 #define CONFIG_SYS_MMC_ENV_DEV 0 442 #define CONFIG_ENV_SIZE 0x2000 443 #elif defined(CONFIG_QSPI_BOOT) 444 #define CONFIG_ENV_IS_IN_SPI_FLASH 445 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 446 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 447 #define CONFIG_ENV_SECT_SIZE 0x10000 448 #else 449 #define CONFIG_ENV_IS_IN_FLASH 450 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 451 #define CONFIG_ENV_SECT_SIZE 0x20000 452 #define CONFIG_ENV_SIZE 0x20000 453 #endif 454 455 #define CONFIG_CMDLINE_TAG 456 457 #include <asm/fsl_secure_boot.h> 458 459 #endif /* __LS1043AQDS_H__ */ 460