1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 18 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 19 20 #define CONFIG_SKIP_LOWLEVEL_INIT 21 22 #define CONFIG_LAYERSCAPE_NS_ACCESS 23 24 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 25 /* Physical Memory Map */ 26 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 27 #define CONFIG_NR_DRAM_BANKS 2 28 29 #define CONFIG_DDR_SPD 30 #define SPD_EEPROM_ADDRESS 0x51 31 #define CONFIG_SYS_SPD_BUS_NUM 0 32 33 #ifndef CONFIG_SPL 34 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 35 #endif 36 37 #define CONFIG_DDR_ECC 38 #ifdef CONFIG_DDR_ECC 39 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 41 #endif 42 43 #ifdef CONFIG_SYS_DPAA_FMAN 44 #define CONFIG_FMAN_ENET 45 #define CONFIG_PHY_VITESSE 46 #define CONFIG_PHY_REALTEK 47 #define CONFIG_PHYLIB_10G 48 #define RGMII_PHY1_ADDR 0x1 49 #define RGMII_PHY2_ADDR 0x2 50 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 51 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 52 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 53 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 54 /* PHY address on QSGMII riser card on slot 1 */ 55 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 56 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 57 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 58 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 59 /* PHY address on QSGMII riser card on slot 2 */ 60 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 61 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 62 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 63 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 64 #endif 65 66 #ifdef CONFIG_RAMBOOT_PBL 67 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 68 #endif 69 70 #ifdef CONFIG_NAND_BOOT 71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 72 #endif 73 74 #ifdef CONFIG_SD_BOOT 75 #ifdef CONFIG_SD_BOOT_QSPI 76 #define CONFIG_SYS_FSL_PBL_RCW \ 77 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 78 #else 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 80 #endif 81 #endif 82 83 /* LPUART */ 84 #ifdef CONFIG_LPUART 85 #define CONFIG_LPUART_32B_REG 86 #endif 87 88 /* SATA */ 89 #define CONFIG_SCSI_AHCI_PLAT 90 91 /* EEPROM */ 92 #define CONFIG_ID_EEPROM 93 #define CONFIG_SYS_I2C_EEPROM_NXID 94 #define CONFIG_SYS_EEPROM_BUS_NUM 0 95 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 96 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 97 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 98 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 99 100 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 101 102 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 103 #define CONFIG_SYS_SCSI_MAX_LUN 1 104 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 105 CONFIG_SYS_SCSI_MAX_LUN) 106 107 /* 108 * IFC Definitions 109 */ 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 111 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 112 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 113 CSPR_PORT_SIZE_16 | \ 114 CSPR_MSEL_NOR | \ 115 CSPR_V) 116 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 117 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 118 + 0x8000000) | \ 119 CSPR_PORT_SIZE_16 | \ 120 CSPR_MSEL_NOR | \ 121 CSPR_V) 122 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 123 124 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 125 CSOR_NOR_TRHZ_80) 126 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 127 FTIM0_NOR_TEADC(0x5) | \ 128 FTIM0_NOR_TEAHC(0x5)) 129 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 130 FTIM1_NOR_TRAD_NOR(0x1a) | \ 131 FTIM1_NOR_TSEQRAD_NOR(0x13)) 132 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 133 FTIM2_NOR_TCH(0x4) | \ 134 FTIM2_NOR_TWPH(0xe) | \ 135 FTIM2_NOR_TWP(0x1c)) 136 #define CONFIG_SYS_NOR_FTIM3 0 137 138 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 139 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 140 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 141 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 142 143 #define CONFIG_SYS_FLASH_EMPTY_INFO 144 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 145 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 146 147 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 148 #define CONFIG_SYS_WRITE_SWAPPED_DATA 149 150 /* 151 * NAND Flash Definitions 152 */ 153 #define CONFIG_NAND_FSL_IFC 154 155 #define CONFIG_SYS_NAND_BASE 0x7e800000 156 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 157 158 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 159 160 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 161 | CSPR_PORT_SIZE_8 \ 162 | CSPR_MSEL_NAND \ 163 | CSPR_V) 164 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 165 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 166 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 167 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 168 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 169 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 170 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 171 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 172 173 #define CONFIG_SYS_NAND_ONFI_DETECTION 174 175 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 176 FTIM0_NAND_TWP(0x18) | \ 177 FTIM0_NAND_TWCHT(0x7) | \ 178 FTIM0_NAND_TWH(0xa)) 179 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 180 FTIM1_NAND_TWBE(0x39) | \ 181 FTIM1_NAND_TRR(0xe) | \ 182 FTIM1_NAND_TRP(0x18)) 183 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 184 FTIM2_NAND_TREH(0xa) | \ 185 FTIM2_NAND_TWHRE(0x1e)) 186 #define CONFIG_SYS_NAND_FTIM3 0x0 187 188 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 189 #define CONFIG_SYS_MAX_NAND_DEVICE 1 190 #define CONFIG_MTD_NAND_VERIFY_WRITE 191 192 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 193 #endif 194 195 #ifdef CONFIG_NAND_BOOT 196 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 197 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 198 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 199 #endif 200 201 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 202 #define CONFIG_QIXIS_I2C_ACCESS 203 #define CONFIG_SYS_I2C_EARLY_INIT 204 #endif 205 206 /* 207 * QIXIS Definitions 208 */ 209 #define CONFIG_FSL_QIXIS 210 211 #ifdef CONFIG_FSL_QIXIS 212 #define QIXIS_BASE 0x7fb00000 213 #define QIXIS_BASE_PHYS QIXIS_BASE 214 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 215 #define QIXIS_LBMAP_SWITCH 6 216 #define QIXIS_LBMAP_MASK 0x0f 217 #define QIXIS_LBMAP_SHIFT 0 218 #define QIXIS_LBMAP_DFLTBANK 0x00 219 #define QIXIS_LBMAP_ALTBANK 0x04 220 #define QIXIS_LBMAP_NAND 0x09 221 #define QIXIS_LBMAP_SD 0x00 222 #define QIXIS_LBMAP_SD_QSPI 0xff 223 #define QIXIS_LBMAP_QSPI 0xff 224 #define QIXIS_RCW_SRC_NAND 0x106 225 #define QIXIS_RCW_SRC_SD 0x040 226 #define QIXIS_RCW_SRC_QSPI 0x045 227 #define QIXIS_RST_CTL_RESET 0x41 228 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 229 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 230 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 231 232 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 233 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 234 CSPR_PORT_SIZE_8 | \ 235 CSPR_MSEL_GPCM | \ 236 CSPR_V) 237 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 238 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 239 CSOR_NOR_NOR_MODE_AVD_NOR | \ 240 CSOR_NOR_TRHZ_80) 241 242 /* 243 * QIXIS Timing parameters for IFC GPCM 244 */ 245 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 246 FTIM0_GPCM_TEADC(0x20) | \ 247 FTIM0_GPCM_TEAHC(0x10)) 248 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 249 FTIM1_GPCM_TRAD(0x1f)) 250 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 251 FTIM2_GPCM_TCH(0x8) | \ 252 FTIM2_GPCM_TWP(0xf0)) 253 #define CONFIG_SYS_FPGA_FTIM3 0x0 254 #endif 255 256 #ifdef CONFIG_NAND_BOOT 257 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 258 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 259 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 260 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 261 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 262 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 263 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 264 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 265 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 266 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 267 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 268 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 269 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 270 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 271 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 272 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 273 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 274 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 275 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 276 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 277 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 278 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 279 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 280 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 281 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 282 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 283 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 284 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 285 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 286 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 287 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 288 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 289 #else 290 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 299 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 300 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 307 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 308 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 309 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 310 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 311 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 312 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 313 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 314 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 315 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 316 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 317 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 318 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 319 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 320 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 321 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 322 #endif 323 324 /* 325 * I2C bus multiplexer 326 */ 327 #define I2C_MUX_PCA_ADDR_PRI 0x77 328 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 329 #define I2C_RETIMER_ADDR 0x18 330 #define I2C_MUX_CH_DEFAULT 0x8 331 #define I2C_MUX_CH_CH7301 0xC 332 #define I2C_MUX_CH5 0xD 333 #define I2C_MUX_CH7 0xF 334 335 #define I2C_MUX_CH_VOL_MONITOR 0xa 336 337 /* Voltage monitor on channel 2*/ 338 #define I2C_VOL_MONITOR_ADDR 0x40 339 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 340 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 341 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 342 343 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 344 #ifndef CONFIG_SPL_BUILD 345 #define CONFIG_VID 346 #endif 347 #define CONFIG_VOL_MONITOR_IR36021_SET 348 #define CONFIG_VOL_MONITOR_INA220 349 /* The lowest and highest voltage allowed for LS1043AQDS */ 350 #define VDD_MV_MIN 819 351 #define VDD_MV_MAX 1212 352 353 /* QSPI device */ 354 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 355 #define CONFIG_FSL_QSPI 356 #ifdef CONFIG_FSL_QSPI 357 #define CONFIG_SPI_FLASH_SPANSION 358 #define FSL_QSPI_FLASH_SIZE (1 << 24) 359 #define FSL_QSPI_FLASH_NUM 2 360 #endif 361 #endif 362 363 /* 364 * Miscellaneous configurable options 365 */ 366 #define CONFIG_MISC_INIT_R 367 368 #define CONFIG_SYS_MEMTEST_START 0x80000000 369 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 370 371 #define CONFIG_SYS_HZ 1000 372 373 #define CONFIG_SYS_INIT_SP_OFFSET \ 374 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 375 376 #ifdef CONFIG_SPL_BUILD 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 378 #else 379 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 380 #endif 381 382 /* 383 * Environment 384 */ 385 #define CONFIG_ENV_OVERWRITE 386 387 #ifdef CONFIG_NAND_BOOT 388 #define CONFIG_ENV_SIZE 0x2000 389 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) 390 #elif defined(CONFIG_SD_BOOT) 391 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 392 #define CONFIG_SYS_MMC_ENV_DEV 0 393 #define CONFIG_ENV_SIZE 0x2000 394 #elif defined(CONFIG_QSPI_BOOT) 395 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 396 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 397 #define CONFIG_ENV_SECT_SIZE 0x10000 398 #else 399 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 400 #define CONFIG_ENV_SECT_SIZE 0x20000 401 #define CONFIG_ENV_SIZE 0x20000 402 #endif 403 404 #define CONFIG_CMDLINE_TAG 405 406 #include <asm/fsl_secure_boot.h> 407 408 #endif /* __LS1043AQDS_H__ */ 409