1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40010000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 42 43 #define CONFIG_DDR_ECC 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 #ifdef CONFIG_SYS_DPAA_FMAN 50 #define CONFIG_FMAN_ENET 51 #define CONFIG_PHYLIB 52 #define CONFIG_PHY_VITESSE 53 #define CONFIG_PHY_REALTEK 54 #define CONFIG_PHYLIB_10G 55 #define RGMII_PHY1_ADDR 0x1 56 #define RGMII_PHY2_ADDR 0x2 57 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 58 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 59 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 60 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 61 /* PHY address on QSGMII riser card on slot 1 */ 62 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 63 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 64 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 65 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 66 /* PHY address on QSGMII riser card on slot 2 */ 67 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 68 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 69 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 70 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 71 #endif 72 73 #ifdef CONFIG_RAMBOOT_PBL 74 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 75 #endif 76 77 #ifdef CONFIG_NAND_BOOT 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 79 #endif 80 81 #ifdef CONFIG_SD_BOOT 82 #ifdef CONFIG_SD_BOOT_QSPI 83 #define CONFIG_SYS_FSL_PBL_RCW \ 84 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 85 #else 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 87 #endif 88 #endif 89 90 /* LPUART */ 91 #ifdef CONFIG_LPUART 92 #define CONFIG_LPUART_32B_REG 93 #endif 94 95 /* SATA */ 96 #define CONFIG_LIBATA 97 #define CONFIG_SCSI_AHCI 98 #define CONFIG_SCSI_AHCI_PLAT 99 #define CONFIG_SCSI 100 #define CONFIG_DOS_PARTITION 101 #define CONFIG_BOARD_LATE_INIT 102 103 #define CONFIG_PARTITION_UUIDS 104 #define CONFIG_EFI_PARTITION 105 #define CONFIG_CMD_GPT 106 107 /* EEPROM */ 108 #define CONFIG_ID_EEPROM 109 #define CONFIG_SYS_I2C_EEPROM_NXID 110 #define CONFIG_SYS_EEPROM_BUS_NUM 0 111 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 112 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 113 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 115 116 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 117 118 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 119 #define CONFIG_SYS_SCSI_MAX_LUN 1 120 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 121 CONFIG_SYS_SCSI_MAX_LUN) 122 123 /* 124 * IFC Definitions 125 */ 126 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 127 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 128 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 129 CSPR_PORT_SIZE_16 | \ 130 CSPR_MSEL_NOR | \ 131 CSPR_V) 132 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 133 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 134 + 0x8000000) | \ 135 CSPR_PORT_SIZE_16 | \ 136 CSPR_MSEL_NOR | \ 137 CSPR_V) 138 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 139 140 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 141 CSOR_NOR_TRHZ_80) 142 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 143 FTIM0_NOR_TEADC(0x5) | \ 144 FTIM0_NOR_TEAHC(0x5)) 145 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 146 FTIM1_NOR_TRAD_NOR(0x1a) | \ 147 FTIM1_NOR_TSEQRAD_NOR(0x13)) 148 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 149 FTIM2_NOR_TCH(0x4) | \ 150 FTIM2_NOR_TWPH(0xe) | \ 151 FTIM2_NOR_TWP(0x1c)) 152 #define CONFIG_SYS_NOR_FTIM3 0 153 154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 155 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 158 159 #define CONFIG_SYS_FLASH_EMPTY_INFO 160 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 161 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 162 163 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 164 #define CONFIG_SYS_WRITE_SWAPPED_DATA 165 166 /* 167 * NAND Flash Definitions 168 */ 169 #define CONFIG_NAND_FSL_IFC 170 171 #define CONFIG_SYS_NAND_BASE 0x7e800000 172 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 173 174 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 175 176 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_NAND \ 179 | CSPR_V) 180 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 181 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 182 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 183 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 184 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 185 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 186 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 187 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 188 189 #define CONFIG_SYS_NAND_ONFI_DETECTION 190 191 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 192 FTIM0_NAND_TWP(0x18) | \ 193 FTIM0_NAND_TWCHT(0x7) | \ 194 FTIM0_NAND_TWH(0xa)) 195 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 196 FTIM1_NAND_TWBE(0x39) | \ 197 FTIM1_NAND_TRR(0xe) | \ 198 FTIM1_NAND_TRP(0x18)) 199 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 200 FTIM2_NAND_TREH(0xa) | \ 201 FTIM2_NAND_TWHRE(0x1e)) 202 #define CONFIG_SYS_NAND_FTIM3 0x0 203 204 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 205 #define CONFIG_SYS_MAX_NAND_DEVICE 1 206 #define CONFIG_MTD_NAND_VERIFY_WRITE 207 #define CONFIG_CMD_NAND 208 209 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 210 #endif 211 212 #ifdef CONFIG_NAND_BOOT 213 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 214 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 215 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 216 #endif 217 218 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 219 #define CONFIG_QIXIS_I2C_ACCESS 220 #define CONFIG_SYS_I2C_EARLY_INIT 221 #define CONFIG_SYS_NO_FLASH 222 #endif 223 224 /* 225 * QIXIS Definitions 226 */ 227 #define CONFIG_FSL_QIXIS 228 229 #ifdef CONFIG_FSL_QIXIS 230 #define QIXIS_BASE 0x7fb00000 231 #define QIXIS_BASE_PHYS QIXIS_BASE 232 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 233 #define QIXIS_LBMAP_SWITCH 6 234 #define QIXIS_LBMAP_MASK 0x0f 235 #define QIXIS_LBMAP_SHIFT 0 236 #define QIXIS_LBMAP_DFLTBANK 0x00 237 #define QIXIS_LBMAP_ALTBANK 0x04 238 #define QIXIS_LBMAP_NAND 0x09 239 #define QIXIS_LBMAP_SD 0x00 240 #define QIXIS_LBMAP_SD_QSPI 0xff 241 #define QIXIS_LBMAP_QSPI 0xff 242 #define QIXIS_RCW_SRC_NAND 0x106 243 #define QIXIS_RCW_SRC_SD 0x040 244 #define QIXIS_RCW_SRC_QSPI 0x045 245 #define QIXIS_RST_CTL_RESET 0x41 246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 247 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 249 250 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 251 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 252 CSPR_PORT_SIZE_8 | \ 253 CSPR_MSEL_GPCM | \ 254 CSPR_V) 255 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 256 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 257 CSOR_NOR_NOR_MODE_AVD_NOR | \ 258 CSOR_NOR_TRHZ_80) 259 260 /* 261 * QIXIS Timing parameters for IFC GPCM 262 */ 263 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 264 FTIM0_GPCM_TEADC(0x20) | \ 265 FTIM0_GPCM_TEAHC(0x10)) 266 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 267 FTIM1_GPCM_TRAD(0x1f)) 268 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 269 FTIM2_GPCM_TCH(0x8) | \ 270 FTIM2_GPCM_TWP(0xf0)) 271 #define CONFIG_SYS_FPGA_FTIM3 0x0 272 #endif 273 274 #ifdef CONFIG_NAND_BOOT 275 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 276 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 277 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 278 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 279 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 280 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 281 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 282 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 283 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 284 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 285 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 286 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 287 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 288 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 289 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 290 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 291 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 292 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 293 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 294 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 295 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 296 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 297 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 298 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 299 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 300 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 301 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 302 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 303 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 304 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 305 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 306 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 307 #else 308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 332 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 333 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 334 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 335 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 336 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 337 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 338 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 339 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 340 #endif 341 342 /* 343 * I2C bus multiplexer 344 */ 345 #define I2C_MUX_PCA_ADDR_PRI 0x77 346 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 347 #define I2C_RETIMER_ADDR 0x18 348 #define I2C_MUX_CH_DEFAULT 0x8 349 #define I2C_MUX_CH_CH7301 0xC 350 #define I2C_MUX_CH5 0xD 351 #define I2C_MUX_CH7 0xF 352 353 #define I2C_MUX_CH_VOL_MONITOR 0xa 354 355 /* Voltage monitor on channel 2*/ 356 #define I2C_VOL_MONITOR_ADDR 0x40 357 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 358 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 359 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 360 361 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 362 #ifndef CONFIG_SPL_BUILD 363 #define CONFIG_VID 364 #endif 365 #define CONFIG_VOL_MONITOR_IR36021_SET 366 #define CONFIG_VOL_MONITOR_INA220 367 /* The lowest and highest voltage allowed for LS1043AQDS */ 368 #define VDD_MV_MIN 819 369 #define VDD_MV_MAX 1212 370 371 /* QSPI device */ 372 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 373 #define CONFIG_FSL_QSPI 374 #ifdef CONFIG_FSL_QSPI 375 #define CONFIG_SPI_FLASH_SPANSION 376 #define FSL_QSPI_FLASH_SIZE (1 << 24) 377 #define FSL_QSPI_FLASH_NUM 2 378 #endif 379 #endif 380 381 /* USB */ 382 #define CONFIG_HAS_FSL_XHCI_USB 383 #ifdef CONFIG_HAS_FSL_XHCI_USB 384 #define CONFIG_USB_XHCI_FSL 385 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 386 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 387 #endif 388 389 /* 390 * Miscellaneous configurable options 391 */ 392 #define CONFIG_MISC_INIT_R 393 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 394 #define CONFIG_AUTO_COMPLETE 395 #define CONFIG_SYS_PBSIZE \ 396 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 397 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 398 399 #define CONFIG_SYS_MEMTEST_START 0x80000000 400 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 401 402 #define CONFIG_SYS_HZ 1000 403 404 /* 405 * Stack sizes 406 * The stack sizes are set up in start.S using the settings below 407 */ 408 #define CONFIG_STACKSIZE (30 * 1024) 409 410 #define CONFIG_SYS_INIT_SP_OFFSET \ 411 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 412 413 #ifdef CONFIG_SPL_BUILD 414 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 415 #else 416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 417 #endif 418 419 /* 420 * Environment 421 */ 422 #define CONFIG_ENV_OVERWRITE 423 424 #ifdef CONFIG_NAND_BOOT 425 #define CONFIG_ENV_IS_IN_NAND 426 #define CONFIG_ENV_SIZE 0x2000 427 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 428 #elif defined(CONFIG_SD_BOOT) 429 #define CONFIG_ENV_OFFSET (1024 * 1024) 430 #define CONFIG_ENV_IS_IN_MMC 431 #define CONFIG_SYS_MMC_ENV_DEV 0 432 #define CONFIG_ENV_SIZE 0x2000 433 #elif defined(CONFIG_QSPI_BOOT) 434 #define CONFIG_ENV_IS_IN_SPI_FLASH 435 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 436 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 437 #define CONFIG_ENV_SECT_SIZE 0x10000 438 #else 439 #define CONFIG_ENV_IS_IN_FLASH 440 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 441 #define CONFIG_ENV_SECT_SIZE 0x20000 442 #define CONFIG_ENV_SIZE 0x20000 443 #endif 444 445 #define CONFIG_CMDLINE_TAG 446 447 #include <asm/fsl_secure_boot.h> 448 449 #endif /* __LS1043AQDS_H__ */ 450