1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 16 #define CONFIG_SYS_TEXT_BASE 0x82000000 17 #else 18 #define CONFIG_SYS_TEXT_BASE 0x60100000 19 #endif 20 21 #ifndef __ASSEMBLY__ 22 unsigned long get_board_sys_clk(void); 23 unsigned long get_board_ddr_clk(void); 24 #endif 25 26 #define CONFIG_SYS_CLK_FREQ 100000000 27 #define CONFIG_DDR_CLK_FREQ 100000000 28 29 #define CONFIG_SKIP_LOWLEVEL_INIT 30 31 #define CONFIG_LAYERSCAPE_NS_ACCESS 32 33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 34 /* Physical Memory Map */ 35 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 36 #define CONFIG_NR_DRAM_BANKS 1 37 38 #define CONFIG_DDR_SPD 39 #define SPD_EEPROM_ADDRESS 0x51 40 #define CONFIG_SYS_SPD_BUS_NUM 0 41 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #ifndef CONFIG_SYS_FSL_DDR4 44 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 45 #endif 46 47 #define CONFIG_DDR_ECC 48 #ifdef CONFIG_DDR_ECC 49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 51 #endif 52 53 #define CONFIG_SYS_HAS_SERDES 54 55 #ifdef CONFIG_SYS_DPAA_FMAN 56 #define CONFIG_FMAN_ENET 57 #define CONFIG_PHYLIB 58 #define CONFIG_PHY_VITESSE 59 #define CONFIG_PHY_REALTEK 60 #define CONFIG_PHYLIB_10G 61 #define RGMII_PHY1_ADDR 0x1 62 #define RGMII_PHY2_ADDR 0x2 63 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 64 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 65 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 66 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 67 /* PHY address on QSGMII riser card on slot 1 */ 68 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 69 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 70 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 71 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 72 /* PHY address on QSGMII riser card on slot 2 */ 73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 77 #endif 78 79 #ifdef CONFIG_RAMBOOT_PBL 80 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 81 #endif 82 83 #ifdef CONFIG_NAND_BOOT 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 85 #endif 86 87 #ifdef CONFIG_SD_BOOT 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 89 #endif 90 91 /* 92 * IFC Definitions 93 */ 94 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 95 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 96 CSPR_PORT_SIZE_16 | \ 97 CSPR_MSEL_NOR | \ 98 CSPR_V) 99 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 100 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 101 + 0x8000000) | \ 102 CSPR_PORT_SIZE_16 | \ 103 CSPR_MSEL_NOR | \ 104 CSPR_V) 105 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 106 107 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 108 CSOR_NOR_TRHZ_80) 109 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 110 FTIM0_NOR_TEADC(0x5) | \ 111 FTIM0_NOR_TEAHC(0x5)) 112 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 113 FTIM1_NOR_TRAD_NOR(0x1a) | \ 114 FTIM1_NOR_TSEQRAD_NOR(0x13)) 115 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 116 FTIM2_NOR_TCH(0x4) | \ 117 FTIM2_NOR_TWPH(0xe) | \ 118 FTIM2_NOR_TWP(0x1c)) 119 #define CONFIG_SYS_NOR_FTIM3 0 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 123 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 124 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 125 126 #define CONFIG_SYS_FLASH_EMPTY_INFO 127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 128 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 129 130 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 131 #define CONFIG_SYS_WRITE_SWAPPED_DATA 132 133 /* 134 * NAND Flash Definitions 135 */ 136 #define CONFIG_NAND_FSL_IFC 137 138 #define CONFIG_SYS_NAND_BASE 0x7e800000 139 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 140 141 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 142 143 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 144 | CSPR_PORT_SIZE_8 \ 145 | CSPR_MSEL_NAND \ 146 | CSPR_V) 147 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 148 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 149 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 150 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 151 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 152 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 153 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 154 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 155 156 #define CONFIG_SYS_NAND_ONFI_DETECTION 157 158 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 159 FTIM0_NAND_TWP(0x18) | \ 160 FTIM0_NAND_TWCHT(0x7) | \ 161 FTIM0_NAND_TWH(0xa)) 162 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 163 FTIM1_NAND_TWBE(0x39) | \ 164 FTIM1_NAND_TRR(0xe) | \ 165 FTIM1_NAND_TRP(0x18)) 166 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 167 FTIM2_NAND_TREH(0xa) | \ 168 FTIM2_NAND_TWHRE(0x1e)) 169 #define CONFIG_SYS_NAND_FTIM3 0x0 170 171 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 172 #define CONFIG_SYS_MAX_NAND_DEVICE 1 173 #define CONFIG_MTD_NAND_VERIFY_WRITE 174 #define CONFIG_CMD_NAND 175 176 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 177 178 #ifdef CONFIG_NAND_BOOT 179 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 180 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 181 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 182 #endif 183 184 /* 185 * QIXIS Definitions 186 */ 187 #define CONFIG_FSL_QIXIS 188 189 #ifdef CONFIG_FSL_QIXIS 190 #define QIXIS_BASE 0x7fb00000 191 #define QIXIS_BASE_PHYS QIXIS_BASE 192 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 193 #define QIXIS_LBMAP_SWITCH 6 194 #define QIXIS_LBMAP_MASK 0x0f 195 #define QIXIS_LBMAP_SHIFT 0 196 #define QIXIS_LBMAP_DFLTBANK 0x00 197 #define QIXIS_LBMAP_ALTBANK 0x04 198 #define QIXIS_RST_CTL_RESET 0x44 199 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 200 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 201 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 202 203 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 204 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 205 CSPR_PORT_SIZE_8 | \ 206 CSPR_MSEL_GPCM | \ 207 CSPR_V) 208 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 209 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 210 CSOR_NOR_NOR_MODE_AVD_NOR | \ 211 CSOR_NOR_TRHZ_80) 212 213 /* 214 * QIXIS Timing parameters for IFC GPCM 215 */ 216 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 217 FTIM0_GPCM_TEADC(0x20) | \ 218 FTIM0_GPCM_TEAHC(0x10)) 219 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 220 FTIM1_GPCM_TRAD(0x1f)) 221 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 222 FTIM2_GPCM_TCH(0x8) | \ 223 FTIM2_GPCM_TWP(0xf0)) 224 #define CONFIG_SYS_FPGA_FTIM3 0x0 225 #endif 226 227 #ifdef CONFIG_NAND_BOOT 228 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 229 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 230 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 231 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 232 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 233 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 234 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 235 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 236 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 237 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 238 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 239 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 240 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 241 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 242 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 243 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 244 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 245 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 246 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 247 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 248 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 249 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 250 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 252 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 253 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 254 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 255 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 256 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 257 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 258 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 259 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 260 #else 261 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 262 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 263 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 264 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 265 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 266 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 267 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 268 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 269 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 270 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 272 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 273 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 274 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 275 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 276 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 277 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 278 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 279 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 280 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 281 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 282 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 283 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 284 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 285 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 286 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 287 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 288 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 289 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 290 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 291 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 292 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 293 #endif 294 295 /* 296 * I2C bus multiplexer 297 */ 298 #define I2C_MUX_PCA_ADDR_PRI 0x77 299 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 300 #define I2C_RETIMER_ADDR 0x18 301 #define I2C_MUX_CH_DEFAULT 0x8 302 #define I2C_MUX_CH_CH7301 0xC 303 #define I2C_MUX_CH5 0xD 304 #define I2C_MUX_CH7 0xF 305 306 #define I2C_MUX_CH_VOL_MONITOR 0xa 307 308 /* Voltage monitor on channel 2*/ 309 #define I2C_VOL_MONITOR_ADDR 0x40 310 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 311 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 312 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 313 314 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 315 #ifndef CONFIG_SPL_BUILD 316 #define CONFIG_VID 317 #endif 318 #define CONFIG_VOL_MONITOR_IR36021_SET 319 #define CONFIG_VOL_MONITOR_INA220 320 /* The lowest and highest voltage allowed for LS1043AQDS */ 321 #define VDD_MV_MIN 819 322 #define VDD_MV_MAX 1212 323 324 /* 325 * Miscellaneous configurable options 326 */ 327 #define CONFIG_MISC_INIT_R 328 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 329 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 330 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 331 #define CONFIG_SYS_PROMPT "=> " 332 #define CONFIG_AUTO_COMPLETE 333 #define CONFIG_SYS_PBSIZE \ 334 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 335 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 336 337 #define CONFIG_CMD_GREPENV 338 #define CONFIG_CMD_MEMINFO 339 #define CONFIG_CMD_MEMTEST 340 #define CONFIG_SYS_MEMTEST_START 0x80000000 341 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 342 343 #define CONFIG_SYS_HZ 1000 344 345 /* 346 * Stack sizes 347 * The stack sizes are set up in start.S using the settings below 348 */ 349 #define CONFIG_STACKSIZE (30 * 1024) 350 351 #define CONFIG_SYS_INIT_SP_OFFSET \ 352 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 353 354 #ifdef CONFIG_SPL_BUILD 355 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 356 #else 357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 358 #endif 359 360 /* 361 * Environment 362 */ 363 #define CONFIG_ENV_OVERWRITE 364 365 #ifdef CONFIG_NAND_BOOT 366 #define CONFIG_ENV_IS_IN_NAND 367 #define CONFIG_ENV_SIZE 0x2000 368 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 369 #elif defined(CONFIG_SD_BOOT) 370 #define CONFIG_ENV_OFFSET (1024 * 1024) 371 #define CONFIG_ENV_IS_IN_MMC 372 #define CONFIG_SYS_MMC_ENV_DEV 0 373 #define CONFIG_ENV_SIZE 0x2000 374 #else 375 #define CONFIG_ENV_IS_IN_FLASH 376 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 377 #define CONFIG_ENV_SECT_SIZE 0x20000 378 #define CONFIG_ENV_SIZE 0x20000 379 #endif 380 381 #define CONFIG_OF_LIBFDT 382 #define CONFIG_OF_BOARD_SETUP 383 #define CONFIG_CMD_BOOTZ 384 #define CONFIG_CMD_MII 385 #define CONFIG_CMDLINE_TAG 386 387 #endif /* __LS1043AQDS_H__ */ 388