1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13 #define CONFIG_SYS_TEXT_BASE 0x82000000 14 #elif defined(CONFIG_QSPI_BOOT) 15 #define CONFIG_SYS_TEXT_BASE 0x40010000 16 #else 17 #define CONFIG_SYS_TEXT_BASE 0x60100000 18 #endif 19 20 #ifndef __ASSEMBLY__ 21 unsigned long get_board_sys_clk(void); 22 unsigned long get_board_ddr_clk(void); 23 #endif 24 25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 30 #define CONFIG_LAYERSCAPE_NS_ACCESS 31 32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 33 /* Physical Memory Map */ 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 35 #define CONFIG_NR_DRAM_BANKS 2 36 37 #define CONFIG_DDR_SPD 38 #define SPD_EEPROM_ADDRESS 0x51 39 #define CONFIG_SYS_SPD_BUS_NUM 0 40 41 #ifndef CONFIG_SPL 42 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 43 #endif 44 45 #define CONFIG_DDR_ECC 46 #ifdef CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 49 #endif 50 51 #ifdef CONFIG_SYS_DPAA_FMAN 52 #define CONFIG_FMAN_ENET 53 #define CONFIG_PHYLIB 54 #define CONFIG_PHY_VITESSE 55 #define CONFIG_PHY_REALTEK 56 #define CONFIG_PHYLIB_10G 57 #define RGMII_PHY1_ADDR 0x1 58 #define RGMII_PHY2_ADDR 0x2 59 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 60 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 61 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 62 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 63 /* PHY address on QSGMII riser card on slot 1 */ 64 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 65 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 66 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 67 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 68 /* PHY address on QSGMII riser card on slot 2 */ 69 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 70 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 71 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 72 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 73 #endif 74 75 #ifdef CONFIG_RAMBOOT_PBL 76 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 77 #endif 78 79 #ifdef CONFIG_NAND_BOOT 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 81 #endif 82 83 #ifdef CONFIG_SD_BOOT 84 #ifdef CONFIG_SD_BOOT_QSPI 85 #define CONFIG_SYS_FSL_PBL_RCW \ 86 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 87 #else 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 89 #endif 90 #endif 91 92 /* LPUART */ 93 #ifdef CONFIG_LPUART 94 #define CONFIG_LPUART_32B_REG 95 #endif 96 97 /* SATA */ 98 #define CONFIG_LIBATA 99 #define CONFIG_SCSI_AHCI 100 #define CONFIG_SCSI_AHCI_PLAT 101 #define CONFIG_SCSI 102 103 /* EEPROM */ 104 #define CONFIG_ID_EEPROM 105 #define CONFIG_SYS_I2C_EEPROM_NXID 106 #define CONFIG_SYS_EEPROM_BUS_NUM 0 107 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 109 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 111 112 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 113 114 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 115 #define CONFIG_SYS_SCSI_MAX_LUN 1 116 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 117 CONFIG_SYS_SCSI_MAX_LUN) 118 119 /* 120 * IFC Definitions 121 */ 122 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 123 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 124 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 125 CSPR_PORT_SIZE_16 | \ 126 CSPR_MSEL_NOR | \ 127 CSPR_V) 128 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 129 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 130 + 0x8000000) | \ 131 CSPR_PORT_SIZE_16 | \ 132 CSPR_MSEL_NOR | \ 133 CSPR_V) 134 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 135 136 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 137 CSOR_NOR_TRHZ_80) 138 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 139 FTIM0_NOR_TEADC(0x5) | \ 140 FTIM0_NOR_TEAHC(0x5)) 141 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 142 FTIM1_NOR_TRAD_NOR(0x1a) | \ 143 FTIM1_NOR_TSEQRAD_NOR(0x13)) 144 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 145 FTIM2_NOR_TCH(0x4) | \ 146 FTIM2_NOR_TWPH(0xe) | \ 147 FTIM2_NOR_TWP(0x1c)) 148 #define CONFIG_SYS_NOR_FTIM3 0 149 150 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 151 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 152 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 153 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 154 155 #define CONFIG_SYS_FLASH_EMPTY_INFO 156 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 157 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 158 159 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 160 #define CONFIG_SYS_WRITE_SWAPPED_DATA 161 162 /* 163 * NAND Flash Definitions 164 */ 165 #define CONFIG_NAND_FSL_IFC 166 167 #define CONFIG_SYS_NAND_BASE 0x7e800000 168 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 169 170 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 171 172 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 173 | CSPR_PORT_SIZE_8 \ 174 | CSPR_MSEL_NAND \ 175 | CSPR_V) 176 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 177 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 178 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 179 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 180 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 181 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 182 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 183 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 184 185 #define CONFIG_SYS_NAND_ONFI_DETECTION 186 187 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 188 FTIM0_NAND_TWP(0x18) | \ 189 FTIM0_NAND_TWCHT(0x7) | \ 190 FTIM0_NAND_TWH(0xa)) 191 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 192 FTIM1_NAND_TWBE(0x39) | \ 193 FTIM1_NAND_TRR(0xe) | \ 194 FTIM1_NAND_TRP(0x18)) 195 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 196 FTIM2_NAND_TREH(0xa) | \ 197 FTIM2_NAND_TWHRE(0x1e)) 198 #define CONFIG_SYS_NAND_FTIM3 0x0 199 200 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 201 #define CONFIG_SYS_MAX_NAND_DEVICE 1 202 #define CONFIG_MTD_NAND_VERIFY_WRITE 203 #define CONFIG_CMD_NAND 204 205 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 206 #endif 207 208 #ifdef CONFIG_NAND_BOOT 209 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 210 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 211 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 212 #endif 213 214 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 215 #define CONFIG_QIXIS_I2C_ACCESS 216 #define CONFIG_SYS_I2C_EARLY_INIT 217 #endif 218 219 /* 220 * QIXIS Definitions 221 */ 222 #define CONFIG_FSL_QIXIS 223 224 #ifdef CONFIG_FSL_QIXIS 225 #define QIXIS_BASE 0x7fb00000 226 #define QIXIS_BASE_PHYS QIXIS_BASE 227 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 228 #define QIXIS_LBMAP_SWITCH 6 229 #define QIXIS_LBMAP_MASK 0x0f 230 #define QIXIS_LBMAP_SHIFT 0 231 #define QIXIS_LBMAP_DFLTBANK 0x00 232 #define QIXIS_LBMAP_ALTBANK 0x04 233 #define QIXIS_LBMAP_NAND 0x09 234 #define QIXIS_LBMAP_SD 0x00 235 #define QIXIS_LBMAP_SD_QSPI 0xff 236 #define QIXIS_LBMAP_QSPI 0xff 237 #define QIXIS_RCW_SRC_NAND 0x106 238 #define QIXIS_RCW_SRC_SD 0x040 239 #define QIXIS_RCW_SRC_QSPI 0x045 240 #define QIXIS_RST_CTL_RESET 0x41 241 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 242 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 243 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 244 245 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 246 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 247 CSPR_PORT_SIZE_8 | \ 248 CSPR_MSEL_GPCM | \ 249 CSPR_V) 250 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 251 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 252 CSOR_NOR_NOR_MODE_AVD_NOR | \ 253 CSOR_NOR_TRHZ_80) 254 255 /* 256 * QIXIS Timing parameters for IFC GPCM 257 */ 258 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 259 FTIM0_GPCM_TEADC(0x20) | \ 260 FTIM0_GPCM_TEAHC(0x10)) 261 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 262 FTIM1_GPCM_TRAD(0x1f)) 263 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 264 FTIM2_GPCM_TCH(0x8) | \ 265 FTIM2_GPCM_TWP(0xf0)) 266 #define CONFIG_SYS_FPGA_FTIM3 0x0 267 #endif 268 269 #ifdef CONFIG_NAND_BOOT 270 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 278 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 279 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 281 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 286 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 287 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 288 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 289 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 290 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 291 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 292 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 293 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 294 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 295 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 296 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 297 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 298 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 299 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 300 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 301 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 302 #else 303 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 304 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 305 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 306 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 307 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 308 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 309 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 310 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 311 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 312 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 313 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 314 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 315 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 316 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 317 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 318 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 319 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 320 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 321 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 322 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 323 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 324 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 325 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 326 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 327 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 328 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 329 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 330 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 331 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 332 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 333 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 334 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 335 #endif 336 337 /* 338 * I2C bus multiplexer 339 */ 340 #define I2C_MUX_PCA_ADDR_PRI 0x77 341 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 342 #define I2C_RETIMER_ADDR 0x18 343 #define I2C_MUX_CH_DEFAULT 0x8 344 #define I2C_MUX_CH_CH7301 0xC 345 #define I2C_MUX_CH5 0xD 346 #define I2C_MUX_CH7 0xF 347 348 #define I2C_MUX_CH_VOL_MONITOR 0xa 349 350 /* Voltage monitor on channel 2*/ 351 #define I2C_VOL_MONITOR_ADDR 0x40 352 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 353 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 354 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 355 356 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 357 #ifndef CONFIG_SPL_BUILD 358 #define CONFIG_VID 359 #endif 360 #define CONFIG_VOL_MONITOR_IR36021_SET 361 #define CONFIG_VOL_MONITOR_INA220 362 /* The lowest and highest voltage allowed for LS1043AQDS */ 363 #define VDD_MV_MIN 819 364 #define VDD_MV_MAX 1212 365 366 /* QSPI device */ 367 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 368 #define CONFIG_FSL_QSPI 369 #ifdef CONFIG_FSL_QSPI 370 #define CONFIG_SPI_FLASH_SPANSION 371 #define FSL_QSPI_FLASH_SIZE (1 << 24) 372 #define FSL_QSPI_FLASH_NUM 2 373 #endif 374 #endif 375 376 /* USB */ 377 #define CONFIG_HAS_FSL_XHCI_USB 378 #ifdef CONFIG_HAS_FSL_XHCI_USB 379 #define CONFIG_USB_XHCI_FSL 380 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 381 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 382 #endif 383 384 /* 385 * Miscellaneous configurable options 386 */ 387 #define CONFIG_MISC_INIT_R 388 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 389 #define CONFIG_AUTO_COMPLETE 390 #define CONFIG_SYS_PBSIZE \ 391 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 392 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 393 394 #define CONFIG_SYS_MEMTEST_START 0x80000000 395 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 396 397 #define CONFIG_SYS_HZ 1000 398 399 #define CONFIG_SYS_INIT_SP_OFFSET \ 400 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 401 402 #ifdef CONFIG_SPL_BUILD 403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 404 #else 405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 406 #endif 407 408 /* 409 * Environment 410 */ 411 #define CONFIG_ENV_OVERWRITE 412 413 #ifdef CONFIG_NAND_BOOT 414 #define CONFIG_ENV_IS_IN_NAND 415 #define CONFIG_ENV_SIZE 0x2000 416 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 417 #elif defined(CONFIG_SD_BOOT) 418 #define CONFIG_ENV_OFFSET (1024 * 1024) 419 #define CONFIG_ENV_IS_IN_MMC 420 #define CONFIG_SYS_MMC_ENV_DEV 0 421 #define CONFIG_ENV_SIZE 0x2000 422 #elif defined(CONFIG_QSPI_BOOT) 423 #define CONFIG_ENV_IS_IN_SPI_FLASH 424 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 425 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 426 #define CONFIG_ENV_SECT_SIZE 0x10000 427 #else 428 #define CONFIG_ENV_IS_IN_FLASH 429 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 430 #define CONFIG_ENV_SECT_SIZE 0x20000 431 #define CONFIG_ENV_SIZE 0x20000 432 #endif 433 434 #define CONFIG_CMDLINE_TAG 435 436 #include <asm/fsl_secure_boot.h> 437 438 #endif /* __LS1043AQDS_H__ */ 439