1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043AQDS_H__ 8 #define __LS1043AQDS_H__ 9 10 #include "ls1043a_common.h" 11 12 #define CONFIG_DISPLAY_CPUINFO 13 #ifdef CONFIG_QSPI_BOOT 14 #define CONFIG_DISPLAY_BOARDINFO_LATE 15 #else 16 #define CONFIG_DISPLAY_BOARDINFO 17 #endif 18 19 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 20 #define CONFIG_SYS_TEXT_BASE 0x82000000 21 #elif defined(CONFIG_QSPI_BOOT) 22 #define CONFIG_SYS_TEXT_BASE 0x40010000 23 #else 24 #define CONFIG_SYS_TEXT_BASE 0x60100000 25 #endif 26 27 #ifndef __ASSEMBLY__ 28 unsigned long get_board_sys_clk(void); 29 unsigned long get_board_ddr_clk(void); 30 #endif 31 32 #define CONFIG_SYS_CLK_FREQ 100000000 33 #define CONFIG_DDR_CLK_FREQ 100000000 34 35 #define CONFIG_SKIP_LOWLEVEL_INIT 36 37 #define CONFIG_LAYERSCAPE_NS_ACCESS 38 39 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 40 /* Physical Memory Map */ 41 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 42 #define CONFIG_NR_DRAM_BANKS 2 43 44 #define CONFIG_DDR_SPD 45 #define SPD_EEPROM_ADDRESS 0x51 46 #define CONFIG_SYS_SPD_BUS_NUM 0 47 48 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 49 #ifndef CONFIG_SYS_FSL_DDR4 50 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 51 #endif 52 53 #define CONFIG_DDR_ECC 54 #ifdef CONFIG_DDR_ECC 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 56 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 57 #endif 58 59 #define CONFIG_SYS_HAS_SERDES 60 61 #ifdef CONFIG_SYS_DPAA_FMAN 62 #define CONFIG_FMAN_ENET 63 #define CONFIG_PHYLIB 64 #define CONFIG_PHY_VITESSE 65 #define CONFIG_PHY_REALTEK 66 #define CONFIG_PHYLIB_10G 67 #define RGMII_PHY1_ADDR 0x1 68 #define RGMII_PHY2_ADDR 0x2 69 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 70 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 71 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 72 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 73 /* PHY address on QSGMII riser card on slot 1 */ 74 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 75 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 76 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 77 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 78 /* PHY address on QSGMII riser card on slot 2 */ 79 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 80 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 81 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 82 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 83 #endif 84 85 #ifdef CONFIG_RAMBOOT_PBL 86 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 87 #endif 88 89 #ifdef CONFIG_NAND_BOOT 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 91 #endif 92 93 #ifdef CONFIG_SD_BOOT 94 #ifdef CONFIG_SD_BOOT_QSPI 95 #define CONFIG_SYS_FSL_PBL_RCW \ 96 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 97 #else 98 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 99 #endif 100 #endif 101 102 /* LPUART */ 103 #ifdef CONFIG_LPUART 104 #define CONFIG_LPUART_32B_REG 105 #endif 106 107 /* SATA */ 108 #define CONFIG_LIBATA 109 #define CONFIG_SCSI_AHCI 110 #define CONFIG_SCSI_AHCI_PLAT 111 #define CONFIG_CMD_SCSI 112 #define CONFIG_CMD_FAT 113 #define CONFIG_CMD_EXT2 114 #define CONFIG_DOS_PARTITION 115 #define CONFIG_BOARD_LATE_INIT 116 117 118 /* EEPROM */ 119 #define CONFIG_ID_EEPROM 120 #define CONFIG_SYS_I2C_EEPROM_NXID 121 #define CONFIG_SYS_EEPROM_BUS_NUM 0 122 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 126 127 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 128 129 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 130 #define CONFIG_SYS_SCSI_MAX_LUN 1 131 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 132 CONFIG_SYS_SCSI_MAX_LUN) 133 134 /* 135 * IFC Definitions 136 */ 137 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 138 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 139 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 140 CSPR_PORT_SIZE_16 | \ 141 CSPR_MSEL_NOR | \ 142 CSPR_V) 143 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 144 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 145 + 0x8000000) | \ 146 CSPR_PORT_SIZE_16 | \ 147 CSPR_MSEL_NOR | \ 148 CSPR_V) 149 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 150 151 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 152 CSOR_NOR_TRHZ_80) 153 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 154 FTIM0_NOR_TEADC(0x5) | \ 155 FTIM0_NOR_TEAHC(0x5)) 156 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 157 FTIM1_NOR_TRAD_NOR(0x1a) | \ 158 FTIM1_NOR_TSEQRAD_NOR(0x13)) 159 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 160 FTIM2_NOR_TCH(0x4) | \ 161 FTIM2_NOR_TWPH(0xe) | \ 162 FTIM2_NOR_TWP(0x1c)) 163 #define CONFIG_SYS_NOR_FTIM3 0 164 165 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 166 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #define CONFIG_SYS_FLASH_EMPTY_INFO 171 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 172 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 173 174 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 175 #define CONFIG_SYS_WRITE_SWAPPED_DATA 176 177 /* 178 * NAND Flash Definitions 179 */ 180 #define CONFIG_NAND_FSL_IFC 181 182 #define CONFIG_SYS_NAND_BASE 0x7e800000 183 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 184 185 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 186 187 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 188 | CSPR_PORT_SIZE_8 \ 189 | CSPR_MSEL_NAND \ 190 | CSPR_V) 191 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 192 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 193 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 194 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 195 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 196 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 197 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 198 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 199 200 #define CONFIG_SYS_NAND_ONFI_DETECTION 201 202 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 203 FTIM0_NAND_TWP(0x18) | \ 204 FTIM0_NAND_TWCHT(0x7) | \ 205 FTIM0_NAND_TWH(0xa)) 206 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 207 FTIM1_NAND_TWBE(0x39) | \ 208 FTIM1_NAND_TRR(0xe) | \ 209 FTIM1_NAND_TRP(0x18)) 210 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 211 FTIM2_NAND_TREH(0xa) | \ 212 FTIM2_NAND_TWHRE(0x1e)) 213 #define CONFIG_SYS_NAND_FTIM3 0x0 214 215 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 216 #define CONFIG_SYS_MAX_NAND_DEVICE 1 217 #define CONFIG_MTD_NAND_VERIFY_WRITE 218 #define CONFIG_CMD_NAND 219 220 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 221 #endif 222 223 #ifdef CONFIG_NAND_BOOT 224 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 225 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 226 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 227 #endif 228 229 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 230 #define CONFIG_QIXIS_I2C_ACCESS 231 #define CONFIG_SYS_NO_FLASH 232 #undef CONFIG_CMD_IMLS 233 #endif 234 235 /* 236 * QIXIS Definitions 237 */ 238 #define CONFIG_FSL_QIXIS 239 240 #ifdef CONFIG_FSL_QIXIS 241 #define QIXIS_BASE 0x7fb00000 242 #define QIXIS_BASE_PHYS QIXIS_BASE 243 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 244 #define QIXIS_LBMAP_SWITCH 6 245 #define QIXIS_LBMAP_MASK 0x0f 246 #define QIXIS_LBMAP_SHIFT 0 247 #define QIXIS_LBMAP_DFLTBANK 0x00 248 #define QIXIS_LBMAP_ALTBANK 0x04 249 #define QIXIS_LBMAP_NAND 0x09 250 #define QIXIS_LBMAP_SD 0x00 251 #define QIXIS_LBMAP_SD_QSPI 0xff 252 #define QIXIS_LBMAP_QSPI 0xff 253 #define QIXIS_RCW_SRC_NAND 0x106 254 #define QIXIS_RCW_SRC_SD 0x040 255 #define QIXIS_RCW_SRC_QSPI 0x045 256 #define QIXIS_RST_CTL_RESET 0x41 257 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 258 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 259 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 260 261 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 262 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 263 CSPR_PORT_SIZE_8 | \ 264 CSPR_MSEL_GPCM | \ 265 CSPR_V) 266 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 267 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 268 CSOR_NOR_NOR_MODE_AVD_NOR | \ 269 CSOR_NOR_TRHZ_80) 270 271 /* 272 * QIXIS Timing parameters for IFC GPCM 273 */ 274 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 275 FTIM0_GPCM_TEADC(0x20) | \ 276 FTIM0_GPCM_TEAHC(0x10)) 277 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 278 FTIM1_GPCM_TRAD(0x1f)) 279 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 280 FTIM2_GPCM_TCH(0x8) | \ 281 FTIM2_GPCM_TWP(0xf0)) 282 #define CONFIG_SYS_FPGA_FTIM3 0x0 283 #endif 284 285 #ifdef CONFIG_NAND_BOOT 286 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 287 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 288 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 289 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 290 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 291 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 292 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 293 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 294 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 295 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 296 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 297 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 298 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 299 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 300 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 301 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 302 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 303 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 304 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 305 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 306 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 307 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 308 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 309 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 310 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 311 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 312 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 313 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 314 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 315 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 316 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 317 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 318 #else 319 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 320 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 321 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 322 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 323 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 324 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 325 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 326 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 327 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 328 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 329 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 344 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 345 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 346 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 347 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 348 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 349 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 350 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 351 #endif 352 353 /* 354 * I2C bus multiplexer 355 */ 356 #define I2C_MUX_PCA_ADDR_PRI 0x77 357 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 358 #define I2C_RETIMER_ADDR 0x18 359 #define I2C_MUX_CH_DEFAULT 0x8 360 #define I2C_MUX_CH_CH7301 0xC 361 #define I2C_MUX_CH5 0xD 362 #define I2C_MUX_CH7 0xF 363 364 #define I2C_MUX_CH_VOL_MONITOR 0xa 365 366 /* Voltage monitor on channel 2*/ 367 #define I2C_VOL_MONITOR_ADDR 0x40 368 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 369 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 370 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 371 372 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 373 #ifndef CONFIG_SPL_BUILD 374 #define CONFIG_VID 375 #endif 376 #define CONFIG_VOL_MONITOR_IR36021_SET 377 #define CONFIG_VOL_MONITOR_INA220 378 /* The lowest and highest voltage allowed for LS1043AQDS */ 379 #define VDD_MV_MIN 819 380 #define VDD_MV_MAX 1212 381 382 /* QSPI device */ 383 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 384 #define CONFIG_FSL_QSPI 385 #ifdef CONFIG_FSL_QSPI 386 #define CONFIG_SPI_FLASH_SPANSION 387 #define FSL_QSPI_FLASH_SIZE (1 << 24) 388 #define FSL_QSPI_FLASH_NUM 2 389 #endif 390 #endif 391 392 /* USB */ 393 #define CONFIG_HAS_FSL_XHCI_USB 394 #ifdef CONFIG_HAS_FSL_XHCI_USB 395 #define CONFIG_USB_XHCI 396 #define CONFIG_USB_XHCI_FSL 397 #define CONFIG_USB_XHCI_DWC3 398 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 399 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 400 #define CONFIG_CMD_USB 401 #define CONFIG_USB_STORAGE 402 #define CONFIG_CMD_EXT2 403 #endif 404 405 /* 406 * Miscellaneous configurable options 407 */ 408 #define CONFIG_MISC_INIT_R 409 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 410 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 411 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 412 #define CONFIG_SYS_PROMPT "=> " 413 #define CONFIG_AUTO_COMPLETE 414 #define CONFIG_SYS_PBSIZE \ 415 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 416 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 417 418 #define CONFIG_CMD_GREPENV 419 #define CONFIG_CMD_MEMINFO 420 #define CONFIG_CMD_MEMTEST 421 #define CONFIG_SYS_MEMTEST_START 0x80000000 422 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 423 424 #define CONFIG_SYS_HZ 1000 425 426 /* 427 * Stack sizes 428 * The stack sizes are set up in start.S using the settings below 429 */ 430 #define CONFIG_STACKSIZE (30 * 1024) 431 432 #define CONFIG_SYS_INIT_SP_OFFSET \ 433 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 434 435 #ifdef CONFIG_SPL_BUILD 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 437 #else 438 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 439 #endif 440 441 /* 442 * Environment 443 */ 444 #define CONFIG_ENV_OVERWRITE 445 446 #ifdef CONFIG_NAND_BOOT 447 #define CONFIG_ENV_IS_IN_NAND 448 #define CONFIG_ENV_SIZE 0x2000 449 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 450 #elif defined(CONFIG_SD_BOOT) 451 #define CONFIG_ENV_OFFSET (1024 * 1024) 452 #define CONFIG_ENV_IS_IN_MMC 453 #define CONFIG_SYS_MMC_ENV_DEV 0 454 #define CONFIG_ENV_SIZE 0x2000 455 #elif defined(CONFIG_QSPI_BOOT) 456 #define CONFIG_ENV_IS_IN_SPI_FLASH 457 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 458 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 459 #define CONFIG_ENV_SECT_SIZE 0x10000 460 #else 461 #define CONFIG_ENV_IS_IN_FLASH 462 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 463 #define CONFIG_ENV_SECT_SIZE 0x20000 464 #define CONFIG_ENV_SIZE 0x20000 465 #endif 466 467 #define CONFIG_CMD_BOOTZ 468 #define CONFIG_CMD_MII 469 #define CONFIG_CMDLINE_TAG 470 471 #include <asm/fsl_secure_boot.h> 472 473 #endif /* __LS1043AQDS_H__ */ 474