1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1043A_COMMON_H 7 #define __LS1043A_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_FMAN 12 #define SPL_NO_DSPI 13 #define SPL_NO_PCIE 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #define SPL_NO_QE 19 #define SPL_NO_EEPROM 20 #endif 21 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 22 #define SPL_NO_MMC 23 #endif 24 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 25 #define SPL_NO_IFC 26 #endif 27 28 #define CONFIG_REMAKE_ELF 29 #define CONFIG_FSL_LAYERSCAPE 30 #define CONFIG_MP 31 #define CONFIG_GICV2 32 33 #include <asm/arch/stream_id_lsch2.h> 34 #include <asm/arch/config.h> 35 36 /* Link Definitions */ 37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 38 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 41 #define CONFIG_VERY_BIG_RAM 42 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 43 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 44 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 45 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 46 47 #define CPU_RELEASE_ADDR secondary_boot_func 48 49 /* Generic Timer Definitions */ 50 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 51 52 /* Size of malloc() pool */ 53 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 54 55 /* Serial Port */ 56 #define CONFIG_SYS_NS16550_SERIAL 57 #define CONFIG_SYS_NS16550_REG_SIZE 1 58 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 59 60 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 61 62 /* SD boot SPL */ 63 #ifdef CONFIG_SD_BOOT 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 66 #define CONFIG_SPL_TEXT_BASE 0x10000000 67 #define CONFIG_SPL_MAX_SIZE 0x17000 68 #define CONFIG_SPL_STACK 0x1001e000 69 #define CONFIG_SPL_PAD_TO 0x1d000 70 71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 72 CONFIG_SPL_BSS_MAX_SIZE) 73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 74 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 75 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 76 77 #ifdef CONFIG_SECURE_BOOT 78 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 79 /* 80 * HDR would be appended at end of image and copied to DDR along 81 * with U-Boot image. Here u-boot max. size is 512K. So if binary 82 * size increases then increase this size in case of secure boot as 83 * it uses raw u-boot image instead of fit image. 84 */ 85 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 86 #else 87 #define CONFIG_SYS_MONITOR_LEN 0x100000 88 #endif /* ifdef CONFIG_SECURE_BOOT */ 89 #endif 90 91 /* NAND SPL */ 92 #ifdef CONFIG_NAND_BOOT 93 #define CONFIG_SPL_PBL_PAD 94 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 95 #define CONFIG_SPL_TEXT_BASE 0x10000000 96 #define CONFIG_SPL_MAX_SIZE 0x1a000 97 #define CONFIG_SPL_STACK 0x1001d000 98 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 99 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 100 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 101 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 102 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 103 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 104 105 #ifdef CONFIG_SECURE_BOOT 106 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 107 #endif /* ifdef CONFIG_SECURE_BOOT */ 108 109 #ifdef CONFIG_U_BOOT_HDR_SIZE 110 /* 111 * HDR would be appended at end of image and copied to DDR along 112 * with U-Boot image. Here u-boot max. size is 512K. So if binary 113 * size increases then increase this size in case of secure boot as 114 * it uses raw u-boot image instead of fit image. 115 */ 116 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 117 #else 118 #define CONFIG_SYS_MONITOR_LEN 0x100000 119 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 120 121 #endif 122 123 /* IFC */ 124 #ifndef SPL_NO_IFC 125 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 126 #define CONFIG_FSL_IFC 127 /* 128 * CONFIG_SYS_FLASH_BASE has the final address (core view) 129 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 130 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 131 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 132 */ 133 #define CONFIG_SYS_FLASH_BASE 0x60000000 134 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 135 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 136 137 #ifdef CONFIG_MTD_NOR_FLASH 138 #define CONFIG_FLASH_CFI_DRIVER 139 #define CONFIG_SYS_FLASH_CFI 140 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 141 #define CONFIG_SYS_FLASH_QUIET_TEST 142 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 143 #endif 144 #endif 145 #endif 146 147 /* I2C */ 148 #define CONFIG_SYS_I2C 149 150 /* PCIe */ 151 #ifndef SPL_NO_PCIE 152 #define CONFIG_PCIE1 /* PCIE controller 1 */ 153 #define CONFIG_PCIE2 /* PCIE controller 2 */ 154 #define CONFIG_PCIE3 /* PCIE controller 3 */ 155 156 #ifdef CONFIG_PCI 157 #define CONFIG_PCI_SCAN_SHOW 158 #endif 159 #endif 160 161 /* Command line configuration */ 162 163 /* MMC */ 164 #ifndef SPL_NO_MMC 165 #ifdef CONFIG_MMC 166 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 167 #endif 168 #endif 169 170 /* DSPI */ 171 #ifndef SPL_NO_DSPI 172 #define CONFIG_FSL_DSPI 173 #ifdef CONFIG_FSL_DSPI 174 #define CONFIG_DM_SPI_FLASH 175 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 176 #define CONFIG_SPI_FLASH_SST /* cs1 */ 177 #define CONFIG_SPI_FLASH_EON /* cs2 */ 178 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 179 #define CONFIG_SF_DEFAULT_BUS 1 180 #define CONFIG_SF_DEFAULT_CS 0 181 #endif 182 #endif 183 #endif 184 185 /* FMan ucode */ 186 #ifndef SPL_NO_FMAN 187 #define CONFIG_SYS_DPAA_FMAN 188 #ifdef CONFIG_SYS_DPAA_FMAN 189 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 190 191 #ifdef CONFIG_NAND_BOOT 192 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 193 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 194 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 195 #elif defined(CONFIG_SD_BOOT) 196 /* 197 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 198 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 199 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 200 */ 201 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 202 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 203 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 204 #elif defined(CONFIG_QSPI_BOOT) 205 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 206 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 207 #define CONFIG_ENV_SPI_BUS 0 208 #define CONFIG_ENV_SPI_CS 0 209 #define CONFIG_ENV_SPI_MAX_HZ 1000000 210 #define CONFIG_ENV_SPI_MODE 0x03 211 #else 212 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 213 /* FMan fireware Pre-load address */ 214 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 215 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 216 #endif 217 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 218 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 219 #endif 220 #endif 221 222 /* Miscellaneous configurable options */ 223 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 224 225 #define CONFIG_HWCONFIG 226 #define HWCONFIG_BUFFER_SIZE 128 227 228 #ifndef SPL_NO_MISC 229 #ifndef CONFIG_SPL_BUILD 230 #define BOOT_TARGET_DEVICES(func) \ 231 func(MMC, mmc, 0) \ 232 func(USB, usb, 0) 233 #include <config_distro_bootcmd.h> 234 #endif 235 236 /* Initial environment variables */ 237 #define CONFIG_EXTRA_ENV_SETTINGS \ 238 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 239 "fdt_high=0xffffffffffffffff\0" \ 240 "initrd_high=0xffffffffffffffff\0" \ 241 "fdt_addr=0x64f00000\0" \ 242 "kernel_addr=0x61000000\0" \ 243 "scriptaddr=0x80000000\0" \ 244 "scripthdraddr=0x80080000\0" \ 245 "fdtheader_addr_r=0x80100000\0" \ 246 "kernelheader_addr_r=0x80200000\0" \ 247 "kernel_addr_r=0x81000000\0" \ 248 "fdt_addr_r=0x90000000\0" \ 249 "load_addr=0xa0000000\0" \ 250 "kernelheader_addr=0x60800000\0" \ 251 "kernel_size=0x2800000\0" \ 252 "kernelheader_size=0x40000\0" \ 253 "kernel_addr_sd=0x8000\0" \ 254 "kernel_size_sd=0x14000\0" \ 255 "kernelhdr_addr_sd=0x4000\0" \ 256 "kernelhdr_size_sd=0x10\0" \ 257 "console=ttyS0,115200\0" \ 258 "boot_os=y\0" \ 259 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 260 BOOTENV \ 261 "boot_scripts=ls1043ardb_boot.scr\0" \ 262 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 263 "scan_dev_for_boot_part=" \ 264 "part list ${devtype} ${devnum} devplist; " \ 265 "env exists devplist || setenv devplist 1; " \ 266 "for distro_bootpart in ${devplist}; do " \ 267 "if fstype ${devtype} " \ 268 "${devnum}:${distro_bootpart} " \ 269 "bootfstype; then " \ 270 "run scan_dev_for_boot; " \ 271 "fi; " \ 272 "done\0" \ 273 "scan_dev_for_boot=" \ 274 "echo Scanning ${devtype} " \ 275 "${devnum}:${distro_bootpart}...; " \ 276 "for prefix in ${boot_prefixes}; do " \ 277 "run scan_dev_for_scripts; " \ 278 "done;\0" \ 279 "boot_a_script=" \ 280 "load ${devtype} ${devnum}:${distro_bootpart} " \ 281 "${scriptaddr} ${prefix}${script}; " \ 282 "env exists secureboot && load ${devtype} " \ 283 "${devnum}:${distro_bootpart} " \ 284 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 285 "&& esbc_validate ${scripthdraddr};" \ 286 "source ${scriptaddr}\0" \ 287 "qspi_bootcmd=echo Trying load from qspi..;" \ 288 "sf probe && sf read $load_addr " \ 289 "$kernel_addr $kernel_size; env exists secureboot " \ 290 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 291 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 292 "bootm $load_addr#$board\0" \ 293 "nor_bootcmd=echo Trying load from nor..;" \ 294 "cp.b $kernel_addr $load_addr " \ 295 "$kernel_size; env exists secureboot " \ 296 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 297 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 298 "bootm $load_addr#$board\0" \ 299 "sd_bootcmd=echo Trying load from SD ..;" \ 300 "mmcinfo; mmc read $load_addr " \ 301 "$kernel_addr_sd $kernel_size_sd && " \ 302 "env exists secureboot && mmc read $kernelheader_addr_r " \ 303 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 304 " && esbc_validate ${kernelheader_addr_r};" \ 305 "bootm $load_addr#$board\0" 306 307 308 #undef CONFIG_BOOTCOMMAND 309 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 310 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 311 "env exists secureboot && esbc_halt;" 312 #elif defined(CONFIG_SD_BOOT) 313 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 314 "env exists secureboot && esbc_halt;" 315 #else 316 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 317 "env exists secureboot && esbc_halt;" 318 #endif 319 #endif 320 321 /* Monitor Command Prompt */ 322 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 323 324 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 325 326 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 327 328 #include <asm/arch/soc.h> 329 330 #endif /* __LS1043A_COMMON_H */ 331