1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_FMAN 13 #define SPL_NO_DSPI 14 #define SPL_NO_PCIE 15 #define SPL_NO_ENV 16 #define SPL_NO_MISC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QE 20 #define SPL_NO_EEPROM 21 #endif 22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 23 #define SPL_NO_MMC 24 #endif 25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_FSL_LAYERSCAPE 31 #define CONFIG_MP 32 #define CONFIG_GICV2 33 34 #include <asm/arch/stream_id_lsch2.h> 35 #include <asm/arch/config.h> 36 37 /* Link Definitions */ 38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 39 40 #define CONFIG_SUPPORT_RAW_INITRD 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 49 50 #define CPU_RELEASE_ADDR secondary_boot_func 51 52 /* Generic Timer Definitions */ 53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 54 55 /* Size of malloc() pool */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 57 58 /* Serial Port */ 59 #define CONFIG_CONS_INDEX 1 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE 1 62 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 63 64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 65 66 /* SD boot SPL */ 67 #ifdef CONFIG_SD_BOOT 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 70 71 #define CONFIG_SPL_TEXT_BASE 0x10000000 72 #define CONFIG_SPL_MAX_SIZE 0x17000 73 #define CONFIG_SPL_STACK 0x1001e000 74 #define CONFIG_SPL_PAD_TO 0x1d000 75 76 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 77 CONFIG_SYS_MONITOR_LEN) 78 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 79 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 80 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 81 82 #ifdef CONFIG_SECURE_BOOT 83 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 84 /* 85 * HDR would be appended at end of image and copied to DDR along 86 * with U-Boot image. Here u-boot max. size is 512K. So if binary 87 * size increases then increase this size in case of secure boot as 88 * it uses raw u-boot image instead of fit image. 89 */ 90 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 91 #else 92 #define CONFIG_SYS_MONITOR_LEN 0x100000 93 #endif /* ifdef CONFIG_SECURE_BOOT */ 94 #endif 95 96 /* NAND SPL */ 97 #ifdef CONFIG_NAND_BOOT 98 #define CONFIG_SPL_PBL_PAD 99 #define CONFIG_SPL_FRAMEWORK 100 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 101 #define CONFIG_SPL_TEXT_BASE 0x10000000 102 #define CONFIG_SPL_MAX_SIZE 0x1a000 103 #define CONFIG_SPL_STACK 0x1001d000 104 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 106 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 107 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 108 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 109 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 110 111 #ifdef CONFIG_SECURE_BOOT 112 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 113 #endif /* ifdef CONFIG_SECURE_BOOT */ 114 115 #ifdef CONFIG_U_BOOT_HDR_SIZE 116 /* 117 * HDR would be appended at end of image and copied to DDR along 118 * with U-Boot image. Here u-boot max. size is 512K. So if binary 119 * size increases then increase this size in case of secure boot as 120 * it uses raw u-boot image instead of fit image. 121 */ 122 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 123 #else 124 #define CONFIG_SYS_MONITOR_LEN 0x100000 125 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 126 127 #endif 128 129 /* IFC */ 130 #ifndef SPL_NO_IFC 131 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 132 #define CONFIG_FSL_IFC 133 /* 134 * CONFIG_SYS_FLASH_BASE has the final address (core view) 135 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 136 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 137 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 138 */ 139 #define CONFIG_SYS_FLASH_BASE 0x60000000 140 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 141 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 142 143 #ifdef CONFIG_MTD_NOR_FLASH 144 #define CONFIG_FLASH_CFI_DRIVER 145 #define CONFIG_SYS_FLASH_CFI 146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 147 #define CONFIG_SYS_FLASH_QUIET_TEST 148 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 149 #endif 150 #endif 151 #endif 152 153 /* I2C */ 154 #define CONFIG_SYS_I2C 155 #define CONFIG_SYS_I2C_MXC 156 #define CONFIG_SYS_I2C_MXC_I2C1 157 #define CONFIG_SYS_I2C_MXC_I2C2 158 #define CONFIG_SYS_I2C_MXC_I2C3 159 #define CONFIG_SYS_I2C_MXC_I2C4 160 161 /* PCIe */ 162 #ifndef SPL_NO_PCIE 163 #define CONFIG_PCIE1 /* PCIE controller 1 */ 164 #define CONFIG_PCIE2 /* PCIE controller 2 */ 165 #define CONFIG_PCIE3 /* PCIE controller 3 */ 166 167 #ifdef CONFIG_PCI 168 #define CONFIG_NET_MULTI 169 #define CONFIG_PCI_SCAN_SHOW 170 #endif 171 #endif 172 173 /* Command line configuration */ 174 175 /* MMC */ 176 #ifndef SPL_NO_MMC 177 #ifdef CONFIG_MMC 178 #define CONFIG_FSL_ESDHC 179 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 180 #endif 181 #endif 182 183 /* DSPI */ 184 #ifndef SPL_NO_DSPI 185 #define CONFIG_FSL_DSPI 186 #ifdef CONFIG_FSL_DSPI 187 #define CONFIG_DM_SPI_FLASH 188 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 189 #define CONFIG_SPI_FLASH_SST /* cs1 */ 190 #define CONFIG_SPI_FLASH_EON /* cs2 */ 191 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 192 #define CONFIG_SF_DEFAULT_BUS 1 193 #define CONFIG_SF_DEFAULT_CS 0 194 #endif 195 #endif 196 #endif 197 198 /* FMan ucode */ 199 #ifndef SPL_NO_FMAN 200 #define CONFIG_SYS_DPAA_FMAN 201 #ifdef CONFIG_SYS_DPAA_FMAN 202 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 203 204 #ifdef CONFIG_NAND_BOOT 205 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 206 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 207 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 208 #elif defined(CONFIG_SD_BOOT) 209 /* 210 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 211 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 212 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 213 */ 214 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 215 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 216 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 217 #elif defined(CONFIG_QSPI_BOOT) 218 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 219 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 220 #define CONFIG_ENV_SPI_BUS 0 221 #define CONFIG_ENV_SPI_CS 0 222 #define CONFIG_ENV_SPI_MAX_HZ 1000000 223 #define CONFIG_ENV_SPI_MODE 0x03 224 #else 225 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 226 /* FMan fireware Pre-load address */ 227 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 228 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 229 #endif 230 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 231 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 232 #endif 233 #endif 234 235 /* Miscellaneous configurable options */ 236 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 237 238 #define CONFIG_HWCONFIG 239 #define HWCONFIG_BUFFER_SIZE 128 240 241 #ifndef SPL_NO_MISC 242 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 243 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 244 "5m(kernel),1m(dtb),9m(file_system)" 245 #else 246 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ 247 "2m@0x100000(nor_bank0_uboot),"\ 248 "40m@0x1100000(nor_bank0_fit)," \ 249 "7m(nor_bank0_user)," \ 250 "2m@0x4100000(nor_bank4_uboot)," \ 251 "40m@0x5100000(nor_bank4_fit),"\ 252 "-(nor_bank4_user);" \ 253 "7e800000.flash:" \ 254 "1m(nand_uboot),1m(nand_uboot_env)," \ 255 "20m(nand_fit);spi0.0:1m(uboot)," \ 256 "5m(kernel),1m(dtb),9m(file_system)" 257 #endif 258 259 #include <config_distro_defaults.h> 260 #ifndef CONFIG_SPL_BUILD 261 #define BOOT_TARGET_DEVICES(func) \ 262 func(MMC, mmc, 0) \ 263 func(USB, usb, 0) 264 #include <config_distro_bootcmd.h> 265 #endif 266 267 /* Initial environment variables */ 268 #define CONFIG_EXTRA_ENV_SETTINGS \ 269 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 270 "fdt_high=0xffffffffffffffff\0" \ 271 "initrd_high=0xffffffffffffffff\0" \ 272 "fdt_addr=0x64f00000\0" \ 273 "kernel_addr=0x65000000\0" \ 274 "scriptaddr=0x80000000\0" \ 275 "scripthdraddr=0x80080000\0" \ 276 "fdtheader_addr_r=0x80100000\0" \ 277 "kernelheader_addr_r=0x80200000\0" \ 278 "kernel_addr_r=0x81000000\0" \ 279 "fdt_addr_r=0x90000000\0" \ 280 "load_addr=0xa0000000\0" \ 281 "kernel_size=0x2800000\0" \ 282 "console=ttyS0,115200\0" \ 283 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 284 BOOTENV \ 285 "boot_scripts=ls1043ardb_boot.scr\0" \ 286 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 287 "scan_dev_for_boot_part=" \ 288 "part list ${devtype} ${devnum} devplist; " \ 289 "env exists devplist || setenv devplist 1; " \ 290 "for distro_bootpart in ${devplist}; do " \ 291 "if fstype ${devtype} " \ 292 "${devnum}:${distro_bootpart} " \ 293 "bootfstype; then " \ 294 "run scan_dev_for_boot; " \ 295 "fi; " \ 296 "done\0" \ 297 "scan_dev_for_boot=" \ 298 "echo Scanning ${devtype} " \ 299 "${devnum}:${distro_bootpart}...; " \ 300 "for prefix in ${boot_prefixes}; do " \ 301 "run scan_dev_for_scripts; " \ 302 "done;\0" \ 303 "boot_a_script=" \ 304 "load ${devtype} ${devnum}:${distro_bootpart} " \ 305 "${scriptaddr} ${prefix}${script}; " \ 306 "env exists secureboot && load ${devtype} " \ 307 "${devnum}:${distro_bootpart} " \ 308 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 309 "&& esbc_validate ${scripthdraddr};" \ 310 "source ${scriptaddr}\0" \ 311 "installer=load mmc 0:2 $load_addr " \ 312 "/flex_installer_arm64.itb; " \ 313 "bootm $load_addr#ls1043ardb\0" \ 314 "qspi_bootcmd=echo Trying load from qspi..;" \ 315 "sf probe && sf read $load_addr " \ 316 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 317 "nor_bootcmd=echo Trying load from nor..;" \ 318 "cp.b $kernel_addr $load_addr " \ 319 "$kernel_size && bootm $load_addr#$board\0" 320 321 #undef CONFIG_BOOTCOMMAND 322 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 323 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ 324 "&& esbc_halt; run qspi_bootcmd;" 325 #else 326 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ 327 "&& esbc_halt; run nor_bootcmd;" 328 #endif 329 #endif 330 331 /* Monitor Command Prompt */ 332 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 333 #define CONFIG_SYS_LONGHELP 334 335 #ifndef SPL_NO_MISC 336 #ifndef CONFIG_CMDLINE_EDITING 337 #define CONFIG_CMDLINE_EDITING 1 338 #endif 339 #endif 340 341 #define CONFIG_AUTO_COMPLETE 342 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 343 344 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 345 346 #include <asm/arch/soc.h> 347 348 #endif /* __LS1043A_COMMON_H */ 349