1 /*
2  * Copyright (C) 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_FSL_LSCH2
13 #define CONFIG_LS1043A
14 #define CONFIG_MP
15 #define CONFIG_SYS_FSL_CLK
16 #define CONFIG_GICV2
17 
18 #include <asm/arch/config.h>
19 #ifdef CONFIG_SYS_FSL_SRDS_1
20 #define	CONFIG_SYS_HAS_SERDES
21 #endif
22 
23 /* Link Definitions */
24 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
25 
26 #define CONFIG_SUPPORT_RAW_INITRD
27 
28 #define CONFIG_SKIP_LOWLEVEL_INIT
29 #define CONFIG_BOARD_EARLY_INIT_F	1
30 
31 #ifndef CONFIG_SYS_FSL_DDR4
32 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
33 #endif
34 
35 #define CONFIG_VERY_BIG_RAM
36 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
38 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
39 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
40 
41 #define CPU_RELEASE_ADDR               secondary_boot_func
42 
43 /* Generic Timer Definitions */
44 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
45 
46 /* Size of malloc() pool */
47 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
48 
49 /* Serial Port */
50 #define CONFIG_CONS_INDEX		1
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE	1
53 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
54 
55 #define CONFIG_BAUDRATE			115200
56 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
57 
58 /* SD boot SPL */
59 #ifdef CONFIG_SD_BOOT
60 #define CONFIG_SPL_FRAMEWORK
61 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
62 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
63 #define CONFIG_SPL_LIBCOMMON_SUPPORT
64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
65 #define CONFIG_SPL_ENV_SUPPORT
66 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
67 #define CONFIG_SPL_WATCHDOG_SUPPORT
68 #define CONFIG_SPL_I2C_SUPPORT
69 #define CONFIG_SPL_SERIAL_SUPPORT
70 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
71 #define CONFIG_SPL_MMC_SUPPORT
72 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xf0
73 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x500
74 
75 #define CONFIG_SPL_TEXT_BASE		0x10000000
76 #define CONFIG_SPL_MAX_SIZE		0x1d000
77 #define CONFIG_SPL_STACK		0x1001e000
78 #define CONFIG_SPL_PAD_TO		0x1d000
79 
80 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
81 					CONFIG_SYS_MONITOR_LEN)
82 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
83 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
84 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
85 #define CONFIG_SYS_MONITOR_LEN		0xa0000
86 #endif
87 
88 /* NAND SPL */
89 #ifdef CONFIG_NAND_BOOT
90 #define CONFIG_SPL_PBL_PAD
91 #define CONFIG_SPL_FRAMEWORK
92 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
93 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
94 #define CONFIG_SPL_LIBCOMMON_SUPPORT
95 #define CONFIG_SPL_LIBGENERIC_SUPPORT
96 #define CONFIG_SPL_ENV_SUPPORT
97 #define CONFIG_SPL_WATCHDOG_SUPPORT
98 #define CONFIG_SPL_I2C_SUPPORT
99 #define CONFIG_SPL_SERIAL_SUPPORT
100 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
101 #define CONFIG_SPL_NAND_SUPPORT
102 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
103 #define CONFIG_SPL_TEXT_BASE		0x10000000
104 #define CONFIG_SPL_MAX_SIZE		0x1a000
105 #define CONFIG_SPL_STACK		0x1001d000
106 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
107 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
108 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
109 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
110 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
111 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
112 #define CONFIG_SYS_MONITOR_LEN		0xa0000
113 #endif
114 
115 /* IFC */
116 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
117 #define CONFIG_FSL_IFC
118 /*
119  * CONFIG_SYS_FLASH_BASE has the final address (core view)
120  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
121  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
122  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
123  */
124 #define CONFIG_SYS_FLASH_BASE			0x60000000
125 #define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
126 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
127 
128 #ifndef CONFIG_SYS_NO_FLASH
129 #define CONFIG_FLASH_CFI_DRIVER
130 #define CONFIG_SYS_FLASH_CFI
131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
132 #define CONFIG_SYS_FLASH_QUIET_TEST
133 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
134 #endif
135 #endif
136 
137 /* I2C */
138 #define CONFIG_SYS_I2C
139 #define CONFIG_SYS_I2C_MXC
140 #define CONFIG_SYS_I2C_MXC_I2C1
141 #define CONFIG_SYS_I2C_MXC_I2C2
142 #define CONFIG_SYS_I2C_MXC_I2C3
143 #define CONFIG_SYS_I2C_MXC_I2C4
144 
145 /* PCIe */
146 #define CONFIG_PCI		/* Enable PCI/PCIE */
147 #define CONFIG_PCIE1		/* PCIE controller 1 */
148 #define CONFIG_PCIE2		/* PCIE controller 2 */
149 #define CONFIG_PCIE3		/* PCIE controller 3 */
150 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
151 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
152 
153 #define CONFIG_SYS_PCI_64BIT
154 
155 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
156 #define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
157 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
158 #define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
159 
160 #define CONFIG_SYS_PCIE_IO_BUS		0x00000000
161 #define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
162 #define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
163 
164 #define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
165 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
166 #define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
167 
168 #ifdef CONFIG_PCI
169 #define CONFIG_NET_MULTI
170 #define CONFIG_PCI_PNP
171 #define CONFIG_E1000
172 #define CONFIG_PCI_SCAN_SHOW
173 #define CONFIG_CMD_PCI
174 #endif
175 
176 /* Command line configuration */
177 #define CONFIG_CMD_ENV
178 
179 /*  MMC  */
180 #define CONFIG_MMC
181 #ifdef CONFIG_MMC
182 #define CONFIG_FSL_ESDHC
183 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
184 #define CONFIG_GENERIC_MMC
185 #define CONFIG_DOS_PARTITION
186 #endif
187 
188 /*  DSPI  */
189 #define CONFIG_FSL_DSPI
190 #ifdef CONFIG_FSL_DSPI
191 #define CONFIG_DM_SPI_FLASH
192 #define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
193 #define CONFIG_SPI_FLASH_SST		/* cs1 */
194 #define CONFIG_SPI_FLASH_EON		/* cs2 */
195 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
196 #define CONFIG_SF_DEFAULT_BUS		1
197 #define CONFIG_SF_DEFAULT_CS		0
198 #endif
199 #endif
200 
201 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
202 
203 /* FMan ucode */
204 #define CONFIG_SYS_DPAA_FMAN
205 #ifdef CONFIG_SYS_DPAA_FMAN
206 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
207 
208 #ifdef CONFIG_NAND_BOOT
209 /* Store Fman ucode at offeset 0x160000(11 blocks). */
210 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
211 #define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
212 #elif defined(CONFIG_SD_BOOT)
213 /*
214  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
215  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
216  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
217  */
218 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
219 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
220 #elif defined(CONFIG_QSPI_BOOT)
221 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
222 #define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
223 #define CONFIG_ENV_SPI_BUS		0
224 #define CONFIG_ENV_SPI_CS		0
225 #define CONFIG_ENV_SPI_MAX_HZ		1000000
226 #define CONFIG_ENV_SPI_MODE		0x03
227 #else
228 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
229 /* FMan fireware Pre-load address */
230 #define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
231 #endif
232 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
233 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
234 #endif
235 
236 /* Miscellaneous configurable options */
237 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
238 #define CONFIG_ARCH_EARLY_INIT_R
239 #define CONFIG_BOARD_LATE_INIT
240 
241 #define CONFIG_HWCONFIG
242 #define HWCONFIG_BUFFER_SIZE		128
243 
244 /* Initial environment variables */
245 #define CONFIG_EXTRA_ENV_SETTINGS		\
246 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
247 	"loadaddr=0x80100000\0"			\
248 	"kernel_addr=0x100000\0"		\
249 	"ramdisk_addr=0x800000\0"		\
250 	"ramdisk_size=0x2000000\0"		\
251 	"fdt_high=0xffffffffffffffff\0"		\
252 	"initrd_high=0xffffffffffffffff\0"	\
253 	"kernel_start=0x61100000\0"		\
254 	"kernel_load=0xa0000000\0"		\
255 	"kernel_size=0x2800000\0"		\
256 	"console=ttyAMA0,38400n8\0"
257 
258 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
259 					"earlycon=uart8250,mmio,0x21c0500"
260 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
261 #define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
262 					"e0000 f00000 && bootm $kernel_load"
263 #else
264 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
265 					"$kernel_size && bootm $kernel_load"
266 #endif
267 #define CONFIG_BOOTDELAY		10
268 
269 /* Monitor Command Prompt */
270 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
271 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
272 					sizeof(CONFIG_SYS_PROMPT) + 16)
273 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
274 #define CONFIG_SYS_LONGHELP
275 #define CONFIG_CMDLINE_EDITING		1
276 #define CONFIG_AUTO_COMPLETE
277 #define CONFIG_SYS_MAXARGS		64	/* max command args */
278 
279 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
280 
281 /* Hash command with SHA acceleration supported in hardware */
282 #ifdef CONFIG_FSL_CAAM
283 #define CONFIG_CMD_HASH
284 #define CONFIG_SHA_HW_ACCEL
285 #endif
286 
287 #endif /* __LS1043A_COMMON_H */
288