1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_LS1043A 13 #define CONFIG_MP 14 #define CONFIG_GICV2 15 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 21 #define CONFIG_SUPPORT_RAW_INITRD 22 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 25 #define CONFIG_VERY_BIG_RAM 26 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 28 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 29 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 30 31 #define CPU_RELEASE_ADDR secondary_boot_func 32 33 /* Generic Timer Definitions */ 34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 35 36 /* Size of malloc() pool */ 37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 38 39 /* Serial Port */ 40 #define CONFIG_CONS_INDEX 1 41 #define CONFIG_SYS_NS16550_SERIAL 42 #define CONFIG_SYS_NS16550_REG_SIZE 1 43 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 44 45 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 46 47 /* SD boot SPL */ 48 #ifdef CONFIG_SD_BOOT 49 #define CONFIG_SPL_FRAMEWORK 50 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 53 #define CONFIG_SPL_TEXT_BASE 0x10000000 54 #define CONFIG_SPL_MAX_SIZE 0x1d000 55 #define CONFIG_SPL_STACK 0x1001e000 56 #define CONFIG_SPL_PAD_TO 0x1d000 57 58 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 59 CONFIG_SYS_MONITOR_LEN) 60 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 61 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 62 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 63 #define CONFIG_SYS_MONITOR_LEN 0xa0000 64 #endif 65 66 /* NAND SPL */ 67 #ifdef CONFIG_NAND_BOOT 68 #define CONFIG_SPL_PBL_PAD 69 #define CONFIG_SPL_FRAMEWORK 70 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 71 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 72 #define CONFIG_SPL_TEXT_BASE 0x10000000 73 #define CONFIG_SPL_MAX_SIZE 0x1a000 74 #define CONFIG_SPL_STACK 0x1001d000 75 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 76 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 77 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 78 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 79 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 80 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 81 #define CONFIG_SYS_MONITOR_LEN 0xa0000 82 #endif 83 84 /* IFC */ 85 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 86 #define CONFIG_FSL_IFC 87 /* 88 * CONFIG_SYS_FLASH_BASE has the final address (core view) 89 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 90 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 91 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 92 */ 93 #define CONFIG_SYS_FLASH_BASE 0x60000000 94 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 95 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 96 97 #ifdef CONFIG_MTD_NOR_FLASH 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 101 #define CONFIG_SYS_FLASH_QUIET_TEST 102 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 103 #endif 104 #endif 105 106 /* I2C */ 107 #define CONFIG_SYS_I2C 108 #define CONFIG_SYS_I2C_MXC 109 #define CONFIG_SYS_I2C_MXC_I2C1 110 #define CONFIG_SYS_I2C_MXC_I2C2 111 #define CONFIG_SYS_I2C_MXC_I2C3 112 #define CONFIG_SYS_I2C_MXC_I2C4 113 114 /* PCIe */ 115 #define CONFIG_PCIE1 /* PCIE controller 1 */ 116 #define CONFIG_PCIE2 /* PCIE controller 2 */ 117 #define CONFIG_PCIE3 /* PCIE controller 3 */ 118 119 #ifdef CONFIG_PCI 120 #define CONFIG_NET_MULTI 121 #define CONFIG_PCI_SCAN_SHOW 122 #define CONFIG_CMD_PCI 123 #endif 124 125 /* Command line configuration */ 126 #define CONFIG_CMD_ENV 127 128 /* MMC */ 129 #ifdef CONFIG_MMC 130 #define CONFIG_FSL_ESDHC 131 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 132 #endif 133 134 /* DSPI */ 135 #define CONFIG_FSL_DSPI 136 #ifdef CONFIG_FSL_DSPI 137 #define CONFIG_DM_SPI_FLASH 138 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 139 #define CONFIG_SPI_FLASH_SST /* cs1 */ 140 #define CONFIG_SPI_FLASH_EON /* cs2 */ 141 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 142 #define CONFIG_SF_DEFAULT_BUS 1 143 #define CONFIG_SF_DEFAULT_CS 0 144 #endif 145 #endif 146 147 /* FMan ucode */ 148 #define CONFIG_SYS_DPAA_FMAN 149 #ifdef CONFIG_SYS_DPAA_FMAN 150 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 151 152 #ifdef CONFIG_NAND_BOOT 153 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 154 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 155 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 156 #elif defined(CONFIG_SD_BOOT) 157 /* 158 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 159 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 160 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 161 */ 162 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 163 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 164 #elif defined(CONFIG_QSPI_BOOT) 165 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 166 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 167 #define CONFIG_ENV_SPI_BUS 0 168 #define CONFIG_ENV_SPI_CS 0 169 #define CONFIG_ENV_SPI_MAX_HZ 1000000 170 #define CONFIG_ENV_SPI_MODE 0x03 171 #else 172 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 173 /* FMan fireware Pre-load address */ 174 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 175 #endif 176 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 177 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 178 #endif 179 180 /* Miscellaneous configurable options */ 181 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 182 183 #define CONFIG_HWCONFIG 184 #define HWCONFIG_BUFFER_SIZE 128 185 186 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 187 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 188 "5m(kernel),1m(dtb),9m(file_system)" 189 #else 190 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 191 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 192 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 193 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 194 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 195 "40m(nor_bank4_fit);7e800000.flash:" \ 196 "1m(nand_uboot),1m(nand_uboot_env)," \ 197 "20m(nand_fit);spi0.0:1m(uboot)," \ 198 "5m(kernel),1m(dtb),9m(file_system)" 199 #endif 200 201 /* Initial environment variables */ 202 #define CONFIG_EXTRA_ENV_SETTINGS \ 203 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 204 "loadaddr=0x80100000\0" \ 205 "fdt_high=0xffffffffffffffff\0" \ 206 "initrd_high=0xffffffffffffffff\0" \ 207 "kernel_start=0x61100000\0" \ 208 "kernel_load=0xa0000000\0" \ 209 "kernel_size=0x2800000\0" \ 210 "console=ttyS0,115200\0" \ 211 "mtdparts=" MTDPARTS_DEFAULT "\0" 212 213 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 214 "earlycon=uart8250,mmio,0x21c0500 " \ 215 MTDPARTS_DEFAULT 216 217 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 218 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 219 "e0000 f00000 && bootm $kernel_load" 220 #else 221 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 222 "$kernel_size && bootm $kernel_load" 223 #endif 224 225 /* Monitor Command Prompt */ 226 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 227 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 228 sizeof(CONFIG_SYS_PROMPT) + 16) 229 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 230 #define CONFIG_SYS_LONGHELP 231 #define CONFIG_CMDLINE_EDITING 1 232 #define CONFIG_AUTO_COMPLETE 233 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 234 235 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 236 237 /* Hash command with SHA acceleration supported in hardware */ 238 #ifdef CONFIG_FSL_CAAM 239 #define CONFIG_CMD_HASH 240 #define CONFIG_SHA_HW_ACCEL 241 #endif 242 243 #endif /* __LS1043A_COMMON_H */ 244