1 /*
2  * Copyright (C) 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
9 
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_FSL_LSCH2
13 #define CONFIG_LS1043A
14 #define CONFIG_MP
15 #define CONFIG_SYS_FSL_CLK
16 #define CONFIG_GICV2
17 
18 #include <asm/arch/config.h>
19 #ifdef CONFIG_SYS_FSL_SRDS_1
20 #define	CONFIG_SYS_HAS_SERDES
21 #endif
22 
23 /* Link Definitions */
24 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
25 
26 #define CONFIG_SUPPORT_RAW_INITRD
27 
28 #define CONFIG_SKIP_LOWLEVEL_INIT
29 #define CONFIG_BOARD_EARLY_INIT_F	1
30 
31 /* Flat Device Tree Definitions */
32 #define CONFIG_OF_LIBFDT
33 #define CONFIG_OF_BOARD_SETUP
34 
35 /* new uImage format support */
36 #define CONFIG_FIT
37 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
38 
39 #ifndef CONFIG_SYS_FSL_DDR4
40 #define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
41 #endif
42 
43 #define CONFIG_VERY_BIG_RAM
44 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
46 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
47 
48 #define CPU_RELEASE_ADDR               secondary_boot_func
49 
50 /* Generic Timer Definitions */
51 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
52 
53 /* Size of malloc() pool */
54 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
55 
56 /* Serial Port */
57 #define CONFIG_CONS_INDEX		1
58 #define CONFIG_SYS_NS16550
59 #define CONFIG_SYS_NS16550_SERIAL
60 #define CONFIG_SYS_NS16550_REG_SIZE	1
61 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
62 
63 #define CONFIG_BAUDRATE			115200
64 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
65 
66 /* SD boot SPL */
67 #ifdef CONFIG_SD_BOOT
68 #define CONFIG_SPL_FRAMEWORK
69 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
70 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
71 #define CONFIG_SPL_LIBCOMMON_SUPPORT
72 #define CONFIG_SPL_LIBGENERIC_SUPPORT
73 #define CONFIG_SPL_ENV_SUPPORT
74 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
75 #define CONFIG_SPL_WATCHDOG_SUPPORT
76 #define CONFIG_SPL_I2C_SUPPORT
77 #define CONFIG_SPL_SERIAL_SUPPORT
78 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
79 #define CONFIG_SPL_MMC_SUPPORT
80 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xf0
81 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x500
82 
83 #define CONFIG_SPL_TEXT_BASE		0x10000000
84 #define CONFIG_SPL_MAX_SIZE		0x1d000
85 #define CONFIG_SPL_STACK		0x1001e000
86 #define CONFIG_SPL_PAD_TO		0x1d000
87 
88 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
89 					CONFIG_SYS_MONITOR_LEN)
90 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
91 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
92 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
93 #define CONFIG_SYS_MONITOR_LEN		0xa0000
94 #endif
95 
96 /* NAND SPL */
97 #ifdef CONFIG_NAND_BOOT
98 #define CONFIG_SPL_PBL_PAD
99 #define CONFIG_SPL_FRAMEWORK
100 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
101 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
102 #define CONFIG_SPL_LIBCOMMON_SUPPORT
103 #define CONFIG_SPL_LIBGENERIC_SUPPORT
104 #define CONFIG_SPL_ENV_SUPPORT
105 #define CONFIG_SPL_WATCHDOG_SUPPORT
106 #define CONFIG_SPL_I2C_SUPPORT
107 #define CONFIG_SPL_SERIAL_SUPPORT
108 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
109 #define CONFIG_SPL_NAND_SUPPORT
110 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
111 #define CONFIG_SPL_TEXT_BASE		0x10000000
112 #define CONFIG_SPL_MAX_SIZE		0x1a000
113 #define CONFIG_SPL_STACK		0x1001d000
114 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
116 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
117 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
118 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
119 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
120 #define CONFIG_SYS_MONITOR_LEN		0xa0000
121 #endif
122 
123 /* IFC */
124 #define CONFIG_FSL_IFC
125 /*
126  * CONFIG_SYS_FLASH_BASE has the final address (core view)
127  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
128  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
129  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
130  */
131 #define CONFIG_SYS_FLASH_BASE			0x60000000
132 #define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
133 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
134 
135 #ifndef CONFIG_SYS_NO_FLASH
136 #define CONFIG_FLASH_CFI_DRIVER
137 #define CONFIG_SYS_FLASH_CFI
138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
139 #define CONFIG_SYS_FLASH_QUIET_TEST
140 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
141 #endif
142 
143 /* I2C */
144 #define CONFIG_CMD_I2C
145 #define CONFIG_SYS_I2C
146 #define CONFIG_SYS_I2C_MXC
147 #define CONFIG_SYS_I2C_MXC_I2C1
148 #define CONFIG_SYS_I2C_MXC_I2C2
149 #define CONFIG_SYS_I2C_MXC_I2C3
150 #define CONFIG_SYS_I2C_MXC_I2C4
151 
152 /* PCIe */
153 #define CONFIG_PCI		/* Enable PCI/PCIE */
154 #define CONFIG_PCIE1		/* PCIE controller 1 */
155 #define CONFIG_PCIE2		/* PCIE controller 2 */
156 #define CONFIG_PCIE3		/* PCIE controller 3 */
157 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
158 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
159 
160 #define CONFIG_SYS_PCI_64BIT
161 
162 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
163 #define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
164 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
165 #define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
166 
167 #define CONFIG_SYS_PCIE_IO_BUS		0x00000000
168 #define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
169 #define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
170 
171 #define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
172 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
173 #define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
174 
175 #ifdef CONFIG_PCI
176 #define CONFIG_NET_MULTI
177 #define CONFIG_PCI_PNP
178 #define CONFIG_E1000
179 #define CONFIG_PCI_SCAN_SHOW
180 #define CONFIG_CMD_PCI
181 #endif
182 
183 /* Command line configuration */
184 #define CONFIG_CMD_CACHE
185 #define CONFIG_CMD_DHCP
186 #define CONFIG_CMD_ENV
187 #define CONFIG_CMD_PING
188 
189 /*  MMC  */
190 #define CONFIG_MMC
191 #ifdef CONFIG_MMC
192 #define CONFIG_CMD_MMC
193 #define CONFIG_CMD_FAT
194 #define CONFIG_FSL_ESDHC
195 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
196 #define CONFIG_GENERIC_MMC
197 #define CONFIG_DOS_PARTITION
198 #endif
199 
200 /* FMan ucode */
201 #define CONFIG_SYS_DPAA_FMAN
202 #ifdef CONFIG_SYS_DPAA_FMAN
203 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
204 
205 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
206 /* FMan fireware Pre-load address */
207 #define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
208 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
209 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
210 #endif
211 
212 /* Miscellaneous configurable options */
213 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
214 #define CONFIG_ARCH_EARLY_INIT_R
215 #define CONFIG_BOARD_LATE_INIT
216 
217 #define CONFIG_HWCONFIG
218 #define HWCONFIG_BUFFER_SIZE		128
219 
220 /* Initial environment variables */
221 #define CONFIG_EXTRA_ENV_SETTINGS		\
222 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
223 	"loadaddr=0x80100000\0"			\
224 	"kernel_addr=0x100000\0"		\
225 	"ramdisk_addr=0x800000\0"		\
226 	"ramdisk_size=0x2000000\0"		\
227 	"fdt_high=0xffffffffffffffff\0"		\
228 	"initrd_high=0xffffffffffffffff\0"	\
229 	"kernel_start=0x61200000\0"		\
230 	"kernel_load=0x807f0000\0"		\
231 	"kernel_size=0x1000000\0"		\
232 	"console=ttyAMA0,38400n8\0"
233 
234 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
235 					"earlycon=uart8250,0x21c0500,115200"
236 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
237 					"$kernel_size && bootm $kernel_load"
238 #define CONFIG_BOOTDELAY		10
239 
240 /* Monitor Command Prompt */
241 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
242 #define CONFIG_SYS_PROMPT		"=> "
243 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
244 					sizeof(CONFIG_SYS_PROMPT) + 16)
245 #define CONFIG_SYS_HUSH_PARSER
246 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
247 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
248 #define CONFIG_SYS_LONGHELP
249 #define CONFIG_CMDLINE_EDITING		1
250 #define CONFIG_AUTO_COMPLETE
251 #define CONFIG_SYS_MAXARGS		64	/* max command args */
252 
253 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
254 
255 #endif /* __LS1043A_COMMON_H */
256