1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_LS1043A 13 #define CONFIG_MP 14 #define CONFIG_GICV2 15 16 #include <asm/arch/config.h> 17 18 /* Link Definitions */ 19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 20 21 #define CONFIG_SUPPORT_RAW_INITRD 22 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 25 #define CONFIG_VERY_BIG_RAM 26 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 28 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 29 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 30 31 #define CPU_RELEASE_ADDR secondary_boot_func 32 33 /* Generic Timer Definitions */ 34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 35 36 /* Size of malloc() pool */ 37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 38 39 /* Serial Port */ 40 #define CONFIG_CONS_INDEX 1 41 #define CONFIG_SYS_NS16550_SERIAL 42 #define CONFIG_SYS_NS16550_REG_SIZE 1 43 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 44 45 #define CONFIG_BAUDRATE 115200 46 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 47 48 /* SD boot SPL */ 49 #ifdef CONFIG_SD_BOOT 50 #define CONFIG_SPL_FRAMEWORK 51 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 52 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 53 54 #define CONFIG_SPL_TEXT_BASE 0x10000000 55 #define CONFIG_SPL_MAX_SIZE 0x1d000 56 #define CONFIG_SPL_STACK 0x1001e000 57 #define CONFIG_SPL_PAD_TO 0x1d000 58 59 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 60 CONFIG_SYS_MONITOR_LEN) 61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64 #define CONFIG_SYS_MONITOR_LEN 0xa0000 65 #endif 66 67 /* NAND SPL */ 68 #ifdef CONFIG_NAND_BOOT 69 #define CONFIG_SPL_PBL_PAD 70 #define CONFIG_SPL_FRAMEWORK 71 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 72 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 73 #define CONFIG_SPL_TEXT_BASE 0x10000000 74 #define CONFIG_SPL_MAX_SIZE 0x1a000 75 #define CONFIG_SPL_STACK 0x1001d000 76 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 77 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 78 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 79 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 81 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 82 #define CONFIG_SYS_MONITOR_LEN 0xa0000 83 #endif 84 85 /* IFC */ 86 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 87 #define CONFIG_FSL_IFC 88 /* 89 * CONFIG_SYS_FLASH_BASE has the final address (core view) 90 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 91 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 92 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 93 */ 94 #define CONFIG_SYS_FLASH_BASE 0x60000000 95 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 96 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 97 98 #ifndef CONFIG_SYS_NO_FLASH 99 #define CONFIG_FLASH_CFI_DRIVER 100 #define CONFIG_SYS_FLASH_CFI 101 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 102 #define CONFIG_SYS_FLASH_QUIET_TEST 103 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 104 #endif 105 #endif 106 107 /* I2C */ 108 #define CONFIG_SYS_I2C 109 #define CONFIG_SYS_I2C_MXC 110 #define CONFIG_SYS_I2C_MXC_I2C1 111 #define CONFIG_SYS_I2C_MXC_I2C2 112 #define CONFIG_SYS_I2C_MXC_I2C3 113 #define CONFIG_SYS_I2C_MXC_I2C4 114 115 /* PCIe */ 116 #define CONFIG_PCIE1 /* PCIE controller 1 */ 117 #define CONFIG_PCIE2 /* PCIE controller 2 */ 118 #define CONFIG_PCIE3 /* PCIE controller 3 */ 119 120 #ifdef CONFIG_PCI 121 #define CONFIG_NET_MULTI 122 #define CONFIG_PCI_SCAN_SHOW 123 #define CONFIG_CMD_PCI 124 #endif 125 126 /* Command line configuration */ 127 #define CONFIG_CMD_ENV 128 129 /* MMC */ 130 #ifdef CONFIG_MMC 131 #define CONFIG_FSL_ESDHC 132 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 133 #endif 134 135 /* DSPI */ 136 #define CONFIG_FSL_DSPI 137 #ifdef CONFIG_FSL_DSPI 138 #define CONFIG_DM_SPI_FLASH 139 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 140 #define CONFIG_SPI_FLASH_SST /* cs1 */ 141 #define CONFIG_SPI_FLASH_EON /* cs2 */ 142 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 143 #define CONFIG_SF_DEFAULT_BUS 1 144 #define CONFIG_SF_DEFAULT_CS 0 145 #endif 146 #endif 147 148 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 149 150 /* FMan ucode */ 151 #define CONFIG_SYS_DPAA_FMAN 152 #ifdef CONFIG_SYS_DPAA_FMAN 153 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 154 155 #ifdef CONFIG_NAND_BOOT 156 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 157 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 158 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 159 #elif defined(CONFIG_SD_BOOT) 160 /* 161 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 162 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 163 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 164 */ 165 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 166 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 167 #elif defined(CONFIG_QSPI_BOOT) 168 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 169 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 170 #define CONFIG_ENV_SPI_BUS 0 171 #define CONFIG_ENV_SPI_CS 0 172 #define CONFIG_ENV_SPI_MAX_HZ 1000000 173 #define CONFIG_ENV_SPI_MODE 0x03 174 #else 175 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 176 /* FMan fireware Pre-load address */ 177 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 178 #endif 179 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 180 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 181 #endif 182 183 /* Miscellaneous configurable options */ 184 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 185 186 #define CONFIG_HWCONFIG 187 #define HWCONFIG_BUFFER_SIZE 128 188 189 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 190 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 191 "5m(kernel),1m(dtb),9m(file_system)" 192 #else 193 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 194 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 195 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 196 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 197 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 198 "40m(nor_bank4_fit);7e800000.flash:" \ 199 "1m(nand_uboot),1m(nand_uboot_env)," \ 200 "20m(nand_fit);spi0.0:1m(uboot)," \ 201 "5m(kernel),1m(dtb),9m(file_system)" 202 #endif 203 204 /* Initial environment variables */ 205 #define CONFIG_EXTRA_ENV_SETTINGS \ 206 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 207 "loadaddr=0x80100000\0" \ 208 "fdt_high=0xffffffffffffffff\0" \ 209 "initrd_high=0xffffffffffffffff\0" \ 210 "kernel_start=0x61100000\0" \ 211 "kernel_load=0xa0000000\0" \ 212 "kernel_size=0x2800000\0" \ 213 "console=ttyS0,115200\0" \ 214 "mtdparts=" MTDPARTS_DEFAULT "\0" 215 216 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 217 "earlycon=uart8250,mmio,0x21c0500 " \ 218 MTDPARTS_DEFAULT 219 220 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 221 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 222 "e0000 f00000 && bootm $kernel_load" 223 #else 224 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 225 "$kernel_size && bootm $kernel_load" 226 #endif 227 228 /* Monitor Command Prompt */ 229 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 230 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 231 sizeof(CONFIG_SYS_PROMPT) + 16) 232 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 233 #define CONFIG_SYS_LONGHELP 234 #define CONFIG_CMDLINE_EDITING 1 235 #define CONFIG_AUTO_COMPLETE 236 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 237 238 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 239 240 /* Hash command with SHA acceleration supported in hardware */ 241 #ifdef CONFIG_FSL_CAAM 242 #define CONFIG_CMD_HASH 243 #define CONFIG_SHA_HW_ACCEL 244 #endif 245 246 #endif /* __LS1043A_COMMON_H */ 247