1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_FSL_LSCH2 13 #define CONFIG_LS1043A 14 #define CONFIG_MP 15 #define CONFIG_SYS_FSL_CLK 16 #define CONFIG_GICV2 17 18 #include <asm/arch/config.h> 19 #ifdef CONFIG_SYS_FSL_SRDS_1 20 #define CONFIG_SYS_HAS_SERDES 21 #endif 22 23 /* Link Definitions */ 24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 25 26 #define CONFIG_SUPPORT_RAW_INITRD 27 28 #define CONFIG_SKIP_LOWLEVEL_INIT 29 #define CONFIG_BOARD_EARLY_INIT_F 1 30 31 #ifndef CONFIG_SYS_FSL_DDR4 32 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 33 #endif 34 35 #define CONFIG_VERY_BIG_RAM 36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 40 41 #define CPU_RELEASE_ADDR secondary_boot_func 42 43 /* Generic Timer Definitions */ 44 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 45 46 /* Size of malloc() pool */ 47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 48 49 /* Serial Port */ 50 #define CONFIG_CONS_INDEX 1 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE 1 53 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 54 55 #define CONFIG_BAUDRATE 115200 56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 57 58 /* SD boot SPL */ 59 #ifdef CONFIG_SD_BOOT 60 #define CONFIG_SPL_FRAMEWORK 61 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 62 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 63 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 64 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 65 66 #define CONFIG_SPL_TEXT_BASE 0x10000000 67 #define CONFIG_SPL_MAX_SIZE 0x1d000 68 #define CONFIG_SPL_STACK 0x1001e000 69 #define CONFIG_SPL_PAD_TO 0x1d000 70 71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 72 CONFIG_SYS_MONITOR_LEN) 73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 74 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 75 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 76 #define CONFIG_SYS_MONITOR_LEN 0xa0000 77 #endif 78 79 /* NAND SPL */ 80 #ifdef CONFIG_NAND_BOOT 81 #define CONFIG_SPL_PBL_PAD 82 #define CONFIG_SPL_FRAMEWORK 83 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 84 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 85 #define CONFIG_SPL_TEXT_BASE 0x10000000 86 #define CONFIG_SPL_MAX_SIZE 0x1a000 87 #define CONFIG_SPL_STACK 0x1001d000 88 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 89 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 90 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 91 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 92 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 94 #define CONFIG_SYS_MONITOR_LEN 0xa0000 95 #endif 96 97 /* IFC */ 98 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 99 #define CONFIG_FSL_IFC 100 /* 101 * CONFIG_SYS_FLASH_BASE has the final address (core view) 102 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 103 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 104 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 105 */ 106 #define CONFIG_SYS_FLASH_BASE 0x60000000 107 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 108 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 109 110 #ifndef CONFIG_SYS_NO_FLASH 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #define CONFIG_SYS_FLASH_QUIET_TEST 115 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 116 #endif 117 #endif 118 119 /* I2C */ 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_I2C_MXC 122 #define CONFIG_SYS_I2C_MXC_I2C1 123 #define CONFIG_SYS_I2C_MXC_I2C2 124 #define CONFIG_SYS_I2C_MXC_I2C3 125 #define CONFIG_SYS_I2C_MXC_I2C4 126 127 /* PCIe */ 128 #define CONFIG_PCI /* Enable PCI/PCIE */ 129 #define CONFIG_PCIE1 /* PCIE controller 1 */ 130 #define CONFIG_PCIE2 /* PCIE controller 2 */ 131 #define CONFIG_PCIE3 /* PCIE controller 3 */ 132 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 133 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 134 135 #define CONFIG_SYS_PCI_64BIT 136 137 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 138 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 139 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 140 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 141 142 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 143 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 144 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 145 146 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 147 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 148 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 149 150 #ifdef CONFIG_PCI 151 #define CONFIG_NET_MULTI 152 #define CONFIG_PCI_PNP 153 #define CONFIG_E1000 154 #define CONFIG_PCI_SCAN_SHOW 155 #define CONFIG_CMD_PCI 156 #endif 157 158 /* Command line configuration */ 159 #define CONFIG_CMD_ENV 160 #define CONFIG_MENU 161 #define CONFIG_CMD_PXE 162 163 /* MMC */ 164 #define CONFIG_MMC 165 #ifdef CONFIG_MMC 166 #define CONFIG_FSL_ESDHC 167 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 168 #define CONFIG_GENERIC_MMC 169 #define CONFIG_DOS_PARTITION 170 #endif 171 172 /* DSPI */ 173 #define CONFIG_FSL_DSPI 174 #ifdef CONFIG_FSL_DSPI 175 #define CONFIG_DM_SPI_FLASH 176 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 177 #define CONFIG_SPI_FLASH_SST /* cs1 */ 178 #define CONFIG_SPI_FLASH_EON /* cs2 */ 179 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 180 #define CONFIG_SF_DEFAULT_BUS 1 181 #define CONFIG_SF_DEFAULT_CS 0 182 #endif 183 #endif 184 185 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 186 187 /* FMan ucode */ 188 #define CONFIG_SYS_DPAA_FMAN 189 #ifdef CONFIG_SYS_DPAA_FMAN 190 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 191 192 #ifdef CONFIG_NAND_BOOT 193 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 194 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 195 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 196 #elif defined(CONFIG_SD_BOOT) 197 /* 198 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 199 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 200 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 201 */ 202 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 203 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 204 #elif defined(CONFIG_QSPI_BOOT) 205 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 206 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 207 #define CONFIG_ENV_SPI_BUS 0 208 #define CONFIG_ENV_SPI_CS 0 209 #define CONFIG_ENV_SPI_MAX_HZ 1000000 210 #define CONFIG_ENV_SPI_MODE 0x03 211 #else 212 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 213 /* FMan fireware Pre-load address */ 214 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 215 #endif 216 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 217 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 218 #endif 219 220 /* Miscellaneous configurable options */ 221 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 222 #define CONFIG_ARCH_EARLY_INIT_R 223 #define CONFIG_BOARD_LATE_INIT 224 225 #define CONFIG_HWCONFIG 226 #define HWCONFIG_BUFFER_SIZE 128 227 228 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 229 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 230 "5m(kernel),1m(dtb),9m(file_system)" 231 #else 232 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 233 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 234 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 235 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 236 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 237 "40m(nor_bank4_fit);7e800000.flash:" \ 238 "1m(nand_uboot),1m(nand_uboot_env)," \ 239 "20m(nand_fit);spi0.0:1m(uboot)," \ 240 "5m(kernel),1m(dtb),9m(file_system)" 241 #endif 242 243 /* Initial environment variables */ 244 #define CONFIG_EXTRA_ENV_SETTINGS \ 245 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 246 "loadaddr=0x80100000\0" \ 247 "fdt_high=0xffffffffffffffff\0" \ 248 "initrd_high=0xffffffffffffffff\0" \ 249 "kernel_start=0x61100000\0" \ 250 "kernel_load=0xa0000000\0" \ 251 "kernel_size=0x2800000\0" \ 252 "console=ttyS0,115200\0" \ 253 "mtdparts=" MTDPARTS_DEFAULT "\0" 254 255 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 256 "earlycon=uart8250,mmio,0x21c0500 " \ 257 MTDPARTS_DEFAULT 258 259 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 260 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 261 "e0000 f00000 && bootm $kernel_load" 262 #else 263 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 264 "$kernel_size && bootm $kernel_load" 265 #endif 266 267 /* Monitor Command Prompt */ 268 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 269 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 270 sizeof(CONFIG_SYS_PROMPT) + 16) 271 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 272 #define CONFIG_SYS_LONGHELP 273 #define CONFIG_CMDLINE_EDITING 1 274 #define CONFIG_AUTO_COMPLETE 275 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 276 277 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 278 279 /* Hash command with SHA acceleration supported in hardware */ 280 #ifdef CONFIG_FSL_CAAM 281 #define CONFIG_CMD_HASH 282 #define CONFIG_SHA_HW_ACCEL 283 #endif 284 285 #endif /* __LS1043A_COMMON_H */ 286