1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_FMAN 13 #define SPL_NO_DSPI 14 #define SPL_NO_PCIE 15 #define SPL_NO_ENV 16 #define SPL_NO_MISC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QE 20 #define SPL_NO_EEPROM 21 #endif 22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 23 #define SPL_NO_MMC 24 #endif 25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_FSL_LAYERSCAPE 31 #define CONFIG_MP 32 #define CONFIG_GICV2 33 34 #include <asm/arch/stream_id_lsch2.h> 35 #include <asm/arch/config.h> 36 37 /* Link Definitions */ 38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 39 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 42 #define CONFIG_VERY_BIG_RAM 43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 47 48 #define CPU_RELEASE_ADDR secondary_boot_func 49 50 /* Generic Timer Definitions */ 51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 52 53 /* Size of malloc() pool */ 54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 55 56 /* Serial Port */ 57 #define CONFIG_SYS_NS16550_SERIAL 58 #define CONFIG_SYS_NS16550_REG_SIZE 1 59 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 60 61 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 62 63 /* SD boot SPL */ 64 #ifdef CONFIG_SD_BOOT 65 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 66 67 #define CONFIG_SPL_TEXT_BASE 0x10000000 68 #define CONFIG_SPL_MAX_SIZE 0x17000 69 #define CONFIG_SPL_STACK 0x1001e000 70 #define CONFIG_SPL_PAD_TO 0x1d000 71 72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 73 CONFIG_SPL_BSS_MAX_SIZE) 74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 76 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 77 78 #ifdef CONFIG_SECURE_BOOT 79 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 80 /* 81 * HDR would be appended at end of image and copied to DDR along 82 * with U-Boot image. Here u-boot max. size is 512K. So if binary 83 * size increases then increase this size in case of secure boot as 84 * it uses raw u-boot image instead of fit image. 85 */ 86 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 87 #else 88 #define CONFIG_SYS_MONITOR_LEN 0x100000 89 #endif /* ifdef CONFIG_SECURE_BOOT */ 90 #endif 91 92 /* NAND SPL */ 93 #ifdef CONFIG_NAND_BOOT 94 #define CONFIG_SPL_PBL_PAD 95 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 96 #define CONFIG_SPL_TEXT_BASE 0x10000000 97 #define CONFIG_SPL_MAX_SIZE 0x1a000 98 #define CONFIG_SPL_STACK 0x1001d000 99 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 100 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 101 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 102 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 103 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 104 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 105 106 #ifdef CONFIG_SECURE_BOOT 107 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 108 #endif /* ifdef CONFIG_SECURE_BOOT */ 109 110 #ifdef CONFIG_U_BOOT_HDR_SIZE 111 /* 112 * HDR would be appended at end of image and copied to DDR along 113 * with U-Boot image. Here u-boot max. size is 512K. So if binary 114 * size increases then increase this size in case of secure boot as 115 * it uses raw u-boot image instead of fit image. 116 */ 117 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 118 #else 119 #define CONFIG_SYS_MONITOR_LEN 0x100000 120 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 121 122 #endif 123 124 /* IFC */ 125 #ifndef SPL_NO_IFC 126 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 127 #define CONFIG_FSL_IFC 128 /* 129 * CONFIG_SYS_FLASH_BASE has the final address (core view) 130 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 131 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 132 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 133 */ 134 #define CONFIG_SYS_FLASH_BASE 0x60000000 135 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 136 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 137 138 #ifdef CONFIG_MTD_NOR_FLASH 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #define CONFIG_SYS_FLASH_QUIET_TEST 143 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 144 #endif 145 #endif 146 #endif 147 148 /* I2C */ 149 #define CONFIG_SYS_I2C 150 #define CONFIG_SYS_I2C_MXC 151 #define CONFIG_SYS_I2C_MXC_I2C1 152 #define CONFIG_SYS_I2C_MXC_I2C2 153 #define CONFIG_SYS_I2C_MXC_I2C3 154 #define CONFIG_SYS_I2C_MXC_I2C4 155 156 /* PCIe */ 157 #ifndef SPL_NO_PCIE 158 #define CONFIG_PCIE1 /* PCIE controller 1 */ 159 #define CONFIG_PCIE2 /* PCIE controller 2 */ 160 #define CONFIG_PCIE3 /* PCIE controller 3 */ 161 162 #ifdef CONFIG_PCI 163 #define CONFIG_PCI_SCAN_SHOW 164 #endif 165 #endif 166 167 /* Command line configuration */ 168 169 /* MMC */ 170 #ifndef SPL_NO_MMC 171 #ifdef CONFIG_MMC 172 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 173 #endif 174 #endif 175 176 /* DSPI */ 177 #ifndef SPL_NO_DSPI 178 #define CONFIG_FSL_DSPI 179 #ifdef CONFIG_FSL_DSPI 180 #define CONFIG_DM_SPI_FLASH 181 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 182 #define CONFIG_SPI_FLASH_SST /* cs1 */ 183 #define CONFIG_SPI_FLASH_EON /* cs2 */ 184 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 185 #define CONFIG_SF_DEFAULT_BUS 1 186 #define CONFIG_SF_DEFAULT_CS 0 187 #endif 188 #endif 189 #endif 190 191 /* FMan ucode */ 192 #ifndef SPL_NO_FMAN 193 #define CONFIG_SYS_DPAA_FMAN 194 #ifdef CONFIG_SYS_DPAA_FMAN 195 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 196 197 #ifdef CONFIG_NAND_BOOT 198 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 199 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 200 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 201 #elif defined(CONFIG_SD_BOOT) 202 /* 203 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 204 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 205 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 206 */ 207 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 208 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 209 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 210 #elif defined(CONFIG_QSPI_BOOT) 211 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 212 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 213 #define CONFIG_ENV_SPI_BUS 0 214 #define CONFIG_ENV_SPI_CS 0 215 #define CONFIG_ENV_SPI_MAX_HZ 1000000 216 #define CONFIG_ENV_SPI_MODE 0x03 217 #else 218 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 219 /* FMan fireware Pre-load address */ 220 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 221 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 222 #endif 223 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 224 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 225 #endif 226 #endif 227 228 /* Miscellaneous configurable options */ 229 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 230 231 #define CONFIG_HWCONFIG 232 #define HWCONFIG_BUFFER_SIZE 128 233 234 #ifndef SPL_NO_MISC 235 #ifndef CONFIG_SPL_BUILD 236 #define BOOT_TARGET_DEVICES(func) \ 237 func(MMC, mmc, 0) \ 238 func(USB, usb, 0) 239 #include <config_distro_bootcmd.h> 240 #endif 241 242 /* Initial environment variables */ 243 #define CONFIG_EXTRA_ENV_SETTINGS \ 244 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 245 "fdt_high=0xffffffffffffffff\0" \ 246 "initrd_high=0xffffffffffffffff\0" \ 247 "fdt_addr=0x64f00000\0" \ 248 "kernel_addr=0x61000000\0" \ 249 "scriptaddr=0x80000000\0" \ 250 "scripthdraddr=0x80080000\0" \ 251 "fdtheader_addr_r=0x80100000\0" \ 252 "kernelheader_addr_r=0x80200000\0" \ 253 "kernel_addr_r=0x81000000\0" \ 254 "fdt_addr_r=0x90000000\0" \ 255 "load_addr=0xa0000000\0" \ 256 "kernelheader_addr=0x60800000\0" \ 257 "kernel_size=0x2800000\0" \ 258 "kernelheader_size=0x40000\0" \ 259 "kernel_addr_sd=0x8000\0" \ 260 "kernel_size_sd=0x14000\0" \ 261 "kernelhdr_addr_sd=0x4000\0" \ 262 "kernelhdr_size_sd=0x10\0" \ 263 "console=ttyS0,115200\0" \ 264 "boot_os=y\0" \ 265 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 266 BOOTENV \ 267 "boot_scripts=ls1043ardb_boot.scr\0" \ 268 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 269 "scan_dev_for_boot_part=" \ 270 "part list ${devtype} ${devnum} devplist; " \ 271 "env exists devplist || setenv devplist 1; " \ 272 "for distro_bootpart in ${devplist}; do " \ 273 "if fstype ${devtype} " \ 274 "${devnum}:${distro_bootpart} " \ 275 "bootfstype; then " \ 276 "run scan_dev_for_boot; " \ 277 "fi; " \ 278 "done\0" \ 279 "scan_dev_for_boot=" \ 280 "echo Scanning ${devtype} " \ 281 "${devnum}:${distro_bootpart}...; " \ 282 "for prefix in ${boot_prefixes}; do " \ 283 "run scan_dev_for_scripts; " \ 284 "done;\0" \ 285 "boot_a_script=" \ 286 "load ${devtype} ${devnum}:${distro_bootpart} " \ 287 "${scriptaddr} ${prefix}${script}; " \ 288 "env exists secureboot && load ${devtype} " \ 289 "${devnum}:${distro_bootpart} " \ 290 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 291 "&& esbc_validate ${scripthdraddr};" \ 292 "source ${scriptaddr}\0" \ 293 "qspi_bootcmd=echo Trying load from qspi..;" \ 294 "sf probe && sf read $load_addr " \ 295 "$kernel_addr $kernel_size; env exists secureboot " \ 296 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 297 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 298 "bootm $load_addr#$board\0" \ 299 "nor_bootcmd=echo Trying load from nor..;" \ 300 "cp.b $kernel_addr $load_addr " \ 301 "$kernel_size; env exists secureboot " \ 302 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 303 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 304 "bootm $load_addr#$board\0" \ 305 "sd_bootcmd=echo Trying load from SD ..;" \ 306 "mmcinfo; mmc read $load_addr " \ 307 "$kernel_addr_sd $kernel_size_sd && " \ 308 "env exists secureboot && mmc read $kernelheader_addr_r " \ 309 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 310 " && esbc_validate ${kernelheader_addr_r};" \ 311 "bootm $load_addr#$board\0" 312 313 314 #undef CONFIG_BOOTCOMMAND 315 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 316 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 317 "env exists secureboot && esbc_halt;" 318 #elif defined(CONFIG_SD_BOOT) 319 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 320 "env exists secureboot && esbc_halt;" 321 #else 322 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 323 "env exists secureboot && esbc_halt;" 324 #endif 325 #endif 326 327 /* Monitor Command Prompt */ 328 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 329 330 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 331 332 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 333 334 #include <asm/arch/soc.h> 335 336 #endif /* __LS1043A_COMMON_H */ 337