1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1043A_COMMON_H 7 #define __LS1043A_COMMON_H 8 9 /* SPL build */ 10 #ifdef CONFIG_SPL_BUILD 11 #define SPL_NO_FMAN 12 #define SPL_NO_DSPI 13 #define SPL_NO_PCIE 14 #define SPL_NO_ENV 15 #define SPL_NO_MISC 16 #define SPL_NO_USB 17 #define SPL_NO_SATA 18 #define SPL_NO_QE 19 #define SPL_NO_EEPROM 20 #endif 21 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 22 #define SPL_NO_MMC 23 #endif 24 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 25 #define SPL_NO_IFC 26 #endif 27 28 #define CONFIG_REMAKE_ELF 29 #define CONFIG_FSL_LAYERSCAPE 30 #define CONFIG_GICV2 31 32 #include <asm/arch/stream_id_lsch2.h> 33 #include <asm/arch/config.h> 34 35 /* Link Definitions */ 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 37 38 #define CONFIG_SKIP_LOWLEVEL_INIT 39 40 #define CONFIG_VERY_BIG_RAM 41 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 42 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 44 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 45 46 #define CPU_RELEASE_ADDR secondary_boot_func 47 48 /* Generic Timer Definitions */ 49 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 50 51 /* Size of malloc() pool */ 52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 53 54 /* Serial Port */ 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE 1 57 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 58 59 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 60 61 /* SD boot SPL */ 62 #ifdef CONFIG_SD_BOOT 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 65 #define CONFIG_SPL_TEXT_BASE 0x10000000 66 #define CONFIG_SPL_MAX_SIZE 0x17000 67 #define CONFIG_SPL_STACK 0x1001e000 68 #define CONFIG_SPL_PAD_TO 0x1d000 69 70 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 71 CONFIG_SPL_BSS_MAX_SIZE) 72 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 73 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 74 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 75 76 #ifdef CONFIG_SECURE_BOOT 77 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 78 /* 79 * HDR would be appended at end of image and copied to DDR along 80 * with U-Boot image. Here u-boot max. size is 512K. So if binary 81 * size increases then increase this size in case of secure boot as 82 * it uses raw u-boot image instead of fit image. 83 */ 84 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 85 #else 86 #define CONFIG_SYS_MONITOR_LEN 0x100000 87 #endif /* ifdef CONFIG_SECURE_BOOT */ 88 #endif 89 90 /* NAND SPL */ 91 #ifdef CONFIG_NAND_BOOT 92 #define CONFIG_SPL_PBL_PAD 93 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 94 #define CONFIG_SPL_TEXT_BASE 0x10000000 95 #define CONFIG_SPL_MAX_SIZE 0x1a000 96 #define CONFIG_SPL_STACK 0x1001d000 97 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 99 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 100 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 101 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 102 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 103 104 #ifdef CONFIG_SECURE_BOOT 105 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 106 #endif /* ifdef CONFIG_SECURE_BOOT */ 107 108 #ifdef CONFIG_U_BOOT_HDR_SIZE 109 /* 110 * HDR would be appended at end of image and copied to DDR along 111 * with U-Boot image. Here u-boot max. size is 512K. So if binary 112 * size increases then increase this size in case of secure boot as 113 * it uses raw u-boot image instead of fit image. 114 */ 115 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 116 #else 117 #define CONFIG_SYS_MONITOR_LEN 0x100000 118 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 119 120 #endif 121 122 /* IFC */ 123 #ifndef SPL_NO_IFC 124 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 125 #define CONFIG_FSL_IFC 126 /* 127 * CONFIG_SYS_FLASH_BASE has the final address (core view) 128 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 129 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 130 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 131 */ 132 #define CONFIG_SYS_FLASH_BASE 0x60000000 133 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 134 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 135 136 #ifdef CONFIG_MTD_NOR_FLASH 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #define CONFIG_SYS_FLASH_QUIET_TEST 141 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 142 #endif 143 #endif 144 #endif 145 146 /* I2C */ 147 #define CONFIG_SYS_I2C 148 149 /* PCIe */ 150 #ifndef SPL_NO_PCIE 151 #define CONFIG_PCIE1 /* PCIE controller 1 */ 152 #define CONFIG_PCIE2 /* PCIE controller 2 */ 153 #define CONFIG_PCIE3 /* PCIE controller 3 */ 154 155 #ifdef CONFIG_PCI 156 #define CONFIG_PCI_SCAN_SHOW 157 #endif 158 #endif 159 160 /* Command line configuration */ 161 162 /* MMC */ 163 #ifndef SPL_NO_MMC 164 #ifdef CONFIG_MMC 165 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 166 #endif 167 #endif 168 169 /* DSPI */ 170 #ifndef SPL_NO_DSPI 171 #define CONFIG_FSL_DSPI 172 #ifdef CONFIG_FSL_DSPI 173 #define CONFIG_DM_SPI_FLASH 174 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 175 #define CONFIG_SPI_FLASH_SST /* cs1 */ 176 #define CONFIG_SPI_FLASH_EON /* cs2 */ 177 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 178 #define CONFIG_SF_DEFAULT_BUS 1 179 #define CONFIG_SF_DEFAULT_CS 0 180 #endif 181 #endif 182 #endif 183 184 /* FMan ucode */ 185 #ifndef SPL_NO_FMAN 186 #define CONFIG_SYS_DPAA_FMAN 187 #ifdef CONFIG_SYS_DPAA_FMAN 188 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 189 190 #ifdef CONFIG_NAND_BOOT 191 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 192 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 193 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 194 #elif defined(CONFIG_SD_BOOT) 195 /* 196 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 197 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 198 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 199 */ 200 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 201 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 202 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 203 #elif defined(CONFIG_QSPI_BOOT) 204 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 205 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 206 #define CONFIG_ENV_SPI_BUS 0 207 #define CONFIG_ENV_SPI_CS 0 208 #define CONFIG_ENV_SPI_MAX_HZ 1000000 209 #define CONFIG_ENV_SPI_MODE 0x03 210 #else 211 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 212 /* FMan fireware Pre-load address */ 213 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 214 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 215 #endif 216 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 217 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 218 #endif 219 #endif 220 221 /* Miscellaneous configurable options */ 222 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 223 224 #define CONFIG_HWCONFIG 225 #define HWCONFIG_BUFFER_SIZE 128 226 227 #ifndef SPL_NO_MISC 228 #ifndef CONFIG_SPL_BUILD 229 #define BOOT_TARGET_DEVICES(func) \ 230 func(MMC, mmc, 0) \ 231 func(USB, usb, 0) 232 #include <config_distro_bootcmd.h> 233 #endif 234 235 /* Initial environment variables */ 236 #define CONFIG_EXTRA_ENV_SETTINGS \ 237 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 238 "fdt_high=0xffffffffffffffff\0" \ 239 "initrd_high=0xffffffffffffffff\0" \ 240 "fdt_addr=0x64f00000\0" \ 241 "kernel_addr=0x61000000\0" \ 242 "scriptaddr=0x80000000\0" \ 243 "scripthdraddr=0x80080000\0" \ 244 "fdtheader_addr_r=0x80100000\0" \ 245 "kernelheader_addr_r=0x80200000\0" \ 246 "kernel_addr_r=0x81000000\0" \ 247 "fdt_addr_r=0x90000000\0" \ 248 "load_addr=0xa0000000\0" \ 249 "kernelheader_addr=0x60800000\0" \ 250 "kernel_size=0x2800000\0" \ 251 "kernelheader_size=0x40000\0" \ 252 "kernel_addr_sd=0x8000\0" \ 253 "kernel_size_sd=0x14000\0" \ 254 "kernelhdr_addr_sd=0x4000\0" \ 255 "kernelhdr_size_sd=0x10\0" \ 256 "console=ttyS0,115200\0" \ 257 "boot_os=y\0" \ 258 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 259 BOOTENV \ 260 "boot_scripts=ls1043ardb_boot.scr\0" \ 261 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 262 "scan_dev_for_boot_part=" \ 263 "part list ${devtype} ${devnum} devplist; " \ 264 "env exists devplist || setenv devplist 1; " \ 265 "for distro_bootpart in ${devplist}; do " \ 266 "if fstype ${devtype} " \ 267 "${devnum}:${distro_bootpart} " \ 268 "bootfstype; then " \ 269 "run scan_dev_for_boot; " \ 270 "fi; " \ 271 "done\0" \ 272 "scan_dev_for_boot=" \ 273 "echo Scanning ${devtype} " \ 274 "${devnum}:${distro_bootpart}...; " \ 275 "for prefix in ${boot_prefixes}; do " \ 276 "run scan_dev_for_scripts; " \ 277 "done;\0" \ 278 "boot_a_script=" \ 279 "load ${devtype} ${devnum}:${distro_bootpart} " \ 280 "${scriptaddr} ${prefix}${script}; " \ 281 "env exists secureboot && load ${devtype} " \ 282 "${devnum}:${distro_bootpart} " \ 283 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 284 "&& esbc_validate ${scripthdraddr};" \ 285 "source ${scriptaddr}\0" \ 286 "qspi_bootcmd=echo Trying load from qspi..;" \ 287 "sf probe && sf read $load_addr " \ 288 "$kernel_addr $kernel_size; env exists secureboot " \ 289 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 290 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 291 "bootm $load_addr#$board\0" \ 292 "nor_bootcmd=echo Trying load from nor..;" \ 293 "cp.b $kernel_addr $load_addr " \ 294 "$kernel_size; env exists secureboot " \ 295 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 296 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 297 "bootm $load_addr#$board\0" \ 298 "sd_bootcmd=echo Trying load from SD ..;" \ 299 "mmcinfo; mmc read $load_addr " \ 300 "$kernel_addr_sd $kernel_size_sd && " \ 301 "env exists secureboot && mmc read $kernelheader_addr_r " \ 302 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 303 " && esbc_validate ${kernelheader_addr_r};" \ 304 "bootm $load_addr#$board\0" 305 306 307 #undef CONFIG_BOOTCOMMAND 308 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 309 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 310 "env exists secureboot && esbc_halt;" 311 #elif defined(CONFIG_SD_BOOT) 312 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 313 "env exists secureboot && esbc_halt;" 314 #else 315 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 316 "env exists secureboot && esbc_halt;" 317 #endif 318 #endif 319 320 /* Monitor Command Prompt */ 321 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 322 323 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 324 325 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 326 327 #include <asm/arch/soc.h> 328 329 #endif /* __LS1043A_COMMON_H */ 330