1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 #define CONFIG_REMAKE_ELF 11 #define CONFIG_FSL_LAYERSCAPE 12 #define CONFIG_LS1043A 13 #define CONFIG_MP 14 #define CONFIG_SYS_FSL_CLK 15 #define CONFIG_GICV2 16 17 #include <asm/arch/config.h> 18 19 /* Link Definitions */ 20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 21 22 #define CONFIG_SUPPORT_RAW_INITRD 23 24 #define CONFIG_SKIP_LOWLEVEL_INIT 25 #define CONFIG_BOARD_EARLY_INIT_F 1 26 27 #define CONFIG_VERY_BIG_RAM 28 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 30 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 32 33 #define CPU_RELEASE_ADDR secondary_boot_func 34 35 /* Generic Timer Definitions */ 36 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 37 38 /* Size of malloc() pool */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 40 41 /* Serial Port */ 42 #define CONFIG_CONS_INDEX 1 43 #define CONFIG_SYS_NS16550_SERIAL 44 #define CONFIG_SYS_NS16550_REG_SIZE 1 45 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 46 47 #define CONFIG_BAUDRATE 115200 48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 49 50 /* SD boot SPL */ 51 #ifdef CONFIG_SD_BOOT 52 #define CONFIG_SPL_FRAMEWORK 53 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 54 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 55 56 #define CONFIG_SPL_TEXT_BASE 0x10000000 57 #define CONFIG_SPL_MAX_SIZE 0x1d000 58 #define CONFIG_SPL_STACK 0x1001e000 59 #define CONFIG_SPL_PAD_TO 0x1d000 60 61 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 62 CONFIG_SYS_MONITOR_LEN) 63 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 64 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 65 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 66 #define CONFIG_SYS_MONITOR_LEN 0xa0000 67 #endif 68 69 /* NAND SPL */ 70 #ifdef CONFIG_NAND_BOOT 71 #define CONFIG_SPL_PBL_PAD 72 #define CONFIG_SPL_FRAMEWORK 73 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 75 #define CONFIG_SPL_TEXT_BASE 0x10000000 76 #define CONFIG_SPL_MAX_SIZE 0x1a000 77 #define CONFIG_SPL_STACK 0x1001d000 78 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 79 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 80 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 84 #define CONFIG_SYS_MONITOR_LEN 0xa0000 85 #endif 86 87 /* IFC */ 88 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 89 #define CONFIG_FSL_IFC 90 /* 91 * CONFIG_SYS_FLASH_BASE has the final address (core view) 92 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 93 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 94 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 95 */ 96 #define CONFIG_SYS_FLASH_BASE 0x60000000 97 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 98 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 99 100 #ifndef CONFIG_SYS_NO_FLASH 101 #define CONFIG_FLASH_CFI_DRIVER 102 #define CONFIG_SYS_FLASH_CFI 103 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104 #define CONFIG_SYS_FLASH_QUIET_TEST 105 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 106 #endif 107 #endif 108 109 /* I2C */ 110 #define CONFIG_SYS_I2C 111 #define CONFIG_SYS_I2C_MXC 112 #define CONFIG_SYS_I2C_MXC_I2C1 113 #define CONFIG_SYS_I2C_MXC_I2C2 114 #define CONFIG_SYS_I2C_MXC_I2C3 115 #define CONFIG_SYS_I2C_MXC_I2C4 116 117 /* PCIe */ 118 #define CONFIG_PCIE1 /* PCIE controller 1 */ 119 #define CONFIG_PCIE2 /* PCIE controller 2 */ 120 #define CONFIG_PCIE3 /* PCIE controller 3 */ 121 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 122 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 123 124 #define CONFIG_SYS_PCI_64BIT 125 126 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 127 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 128 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 129 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 130 131 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 132 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 133 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 134 135 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 136 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 137 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 138 139 #ifdef CONFIG_PCI 140 #define CONFIG_NET_MULTI 141 #define CONFIG_E1000 142 #define CONFIG_PCI_SCAN_SHOW 143 #define CONFIG_CMD_PCI 144 #endif 145 146 /* Command line configuration */ 147 #define CONFIG_CMD_ENV 148 149 /* MMC */ 150 #ifdef CONFIG_MMC 151 #define CONFIG_FSL_ESDHC 152 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 153 #define CONFIG_GENERIC_MMC 154 #define CONFIG_DOS_PARTITION 155 #endif 156 157 /* DSPI */ 158 #define CONFIG_FSL_DSPI 159 #ifdef CONFIG_FSL_DSPI 160 #define CONFIG_DM_SPI_FLASH 161 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 162 #define CONFIG_SPI_FLASH_SST /* cs1 */ 163 #define CONFIG_SPI_FLASH_EON /* cs2 */ 164 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 165 #define CONFIG_SF_DEFAULT_BUS 1 166 #define CONFIG_SF_DEFAULT_CS 0 167 #endif 168 #endif 169 170 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 171 172 /* FMan ucode */ 173 #define CONFIG_SYS_DPAA_FMAN 174 #ifdef CONFIG_SYS_DPAA_FMAN 175 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 176 177 #ifdef CONFIG_NAND_BOOT 178 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 179 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 180 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 181 #elif defined(CONFIG_SD_BOOT) 182 /* 183 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 184 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 185 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 186 */ 187 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 188 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 189 #elif defined(CONFIG_QSPI_BOOT) 190 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 191 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 192 #define CONFIG_ENV_SPI_BUS 0 193 #define CONFIG_ENV_SPI_CS 0 194 #define CONFIG_ENV_SPI_MAX_HZ 1000000 195 #define CONFIG_ENV_SPI_MODE 0x03 196 #else 197 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 198 /* FMan fireware Pre-load address */ 199 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 200 #endif 201 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 202 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 203 #endif 204 205 /* Miscellaneous configurable options */ 206 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 207 #define CONFIG_ARCH_EARLY_INIT_R 208 #define CONFIG_BOARD_LATE_INIT 209 210 #define CONFIG_HWCONFIG 211 #define HWCONFIG_BUFFER_SIZE 128 212 213 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 214 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 215 "5m(kernel),1m(dtb),9m(file_system)" 216 #else 217 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ 218 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ 219 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ 220 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ 221 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ 222 "40m(nor_bank4_fit);7e800000.flash:" \ 223 "1m(nand_uboot),1m(nand_uboot_env)," \ 224 "20m(nand_fit);spi0.0:1m(uboot)," \ 225 "5m(kernel),1m(dtb),9m(file_system)" 226 #endif 227 228 /* Initial environment variables */ 229 #define CONFIG_EXTRA_ENV_SETTINGS \ 230 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 231 "loadaddr=0x80100000\0" \ 232 "fdt_high=0xffffffffffffffff\0" \ 233 "initrd_high=0xffffffffffffffff\0" \ 234 "kernel_start=0x61100000\0" \ 235 "kernel_load=0xa0000000\0" \ 236 "kernel_size=0x2800000\0" \ 237 "console=ttyS0,115200\0" \ 238 "mtdparts=" MTDPARTS_DEFAULT "\0" 239 240 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 241 "earlycon=uart8250,mmio,0x21c0500 " \ 242 MTDPARTS_DEFAULT 243 244 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 245 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 246 "e0000 f00000 && bootm $kernel_load" 247 #else 248 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 249 "$kernel_size && bootm $kernel_load" 250 #endif 251 252 /* Monitor Command Prompt */ 253 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 254 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 255 sizeof(CONFIG_SYS_PROMPT) + 16) 256 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 257 #define CONFIG_SYS_LONGHELP 258 #define CONFIG_CMDLINE_EDITING 1 259 #define CONFIG_AUTO_COMPLETE 260 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 261 262 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 263 264 /* Hash command with SHA acceleration supported in hardware */ 265 #ifdef CONFIG_FSL_CAAM 266 #define CONFIG_CMD_HASH 267 #define CONFIG_SHA_HW_ACCEL 268 #endif 269 270 #endif /* __LS1043A_COMMON_H */ 271