1 /*
2  * Copyright (C) 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
9 
10 /* SPL build */
11 #ifdef CONFIG_SPL_BUILD
12 #define SPL_NO_FMAN
13 #define SPL_NO_DSPI
14 #define SPL_NO_PCIE
15 #define SPL_NO_ENV
16 #define SPL_NO_MISC
17 #define SPL_NO_USB
18 #define SPL_NO_SATA
19 #define SPL_NO_QE
20 #define SPL_NO_EEPROM
21 #endif
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23 #define SPL_NO_MMC
24 #endif
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
26 #define SPL_NO_IFC
27 #endif
28 
29 #define CONFIG_REMAKE_ELF
30 #define CONFIG_FSL_LAYERSCAPE
31 #define CONFIG_MP
32 #define CONFIG_GICV2
33 
34 #include <asm/arch/stream_id_lsch2.h>
35 #include <asm/arch/config.h>
36 
37 /* Link Definitions */
38 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 
40 #define CONFIG_SUPPORT_RAW_INITRD
41 
42 #define CONFIG_SKIP_LOWLEVEL_INIT
43 
44 #define CONFIG_VERY_BIG_RAM
45 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
47 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
48 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
49 
50 #define CPU_RELEASE_ADDR               secondary_boot_func
51 
52 /* Generic Timer Definitions */
53 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
54 
55 /* Size of malloc() pool */
56 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
57 
58 /* Serial Port */
59 #define CONFIG_CONS_INDEX		1
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE	1
62 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
63 
64 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
65 
66 /* SD boot SPL */
67 #ifdef CONFIG_SD_BOOT
68 #define CONFIG_SPL_FRAMEWORK
69 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
70 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
71 
72 #define CONFIG_SPL_TEXT_BASE		0x10000000
73 #define CONFIG_SPL_MAX_SIZE		0x17000
74 #define CONFIG_SPL_STACK		0x1001e000
75 #define CONFIG_SPL_PAD_TO		0x1d000
76 
77 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
78 					CONFIG_SYS_MONITOR_LEN)
79 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
80 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
81 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
82 
83 #ifdef CONFIG_SECURE_BOOT
84 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
85 /*
86  * HDR would be appended at end of image and copied to DDR along
87  * with U-Boot image. Here u-boot max. size is 512K. So if binary
88  * size increases then increase this size in case of secure boot as
89  * it uses raw u-boot image instead of fit image.
90  */
91 #define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
92 #else
93 #define CONFIG_SYS_MONITOR_LEN		0x100000
94 #endif /* ifdef CONFIG_SECURE_BOOT */
95 #endif
96 
97 /* NAND SPL */
98 #ifdef CONFIG_NAND_BOOT
99 #define CONFIG_SPL_PBL_PAD
100 #define CONFIG_SPL_FRAMEWORK
101 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
102 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
103 #define CONFIG_SPL_TEXT_BASE		0x10000000
104 #define CONFIG_SPL_MAX_SIZE		0x1a000
105 #define CONFIG_SPL_STACK		0x1001d000
106 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
107 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
108 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
109 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
110 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
111 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
112 
113 #ifdef CONFIG_SECURE_BOOT
114 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
115 #endif /* ifdef CONFIG_SECURE_BOOT */
116 
117 #ifdef CONFIG_U_BOOT_HDR_SIZE
118 /*
119  * HDR would be appended at end of image and copied to DDR along
120  * with U-Boot image. Here u-boot max. size is 512K. So if binary
121  * size increases then increase this size in case of secure boot as
122  * it uses raw u-boot image instead of fit image.
123  */
124 #define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
125 #else
126 #define CONFIG_SYS_MONITOR_LEN		0x100000
127 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
128 
129 #endif
130 
131 /* IFC */
132 #ifndef SPL_NO_IFC
133 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
134 #define CONFIG_FSL_IFC
135 /*
136  * CONFIG_SYS_FLASH_BASE has the final address (core view)
137  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
138  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
139  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
140  */
141 #define CONFIG_SYS_FLASH_BASE			0x60000000
142 #define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
144 
145 #ifdef CONFIG_MTD_NOR_FLASH
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #define CONFIG_SYS_FLASH_QUIET_TEST
150 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
151 #endif
152 #endif
153 #endif
154 
155 /* I2C */
156 #define CONFIG_SYS_I2C
157 #define CONFIG_SYS_I2C_MXC
158 #define CONFIG_SYS_I2C_MXC_I2C1
159 #define CONFIG_SYS_I2C_MXC_I2C2
160 #define CONFIG_SYS_I2C_MXC_I2C3
161 #define CONFIG_SYS_I2C_MXC_I2C4
162 
163 /* PCIe */
164 #ifndef SPL_NO_PCIE
165 #define CONFIG_PCIE1		/* PCIE controller 1 */
166 #define CONFIG_PCIE2		/* PCIE controller 2 */
167 #define CONFIG_PCIE3		/* PCIE controller 3 */
168 
169 #ifdef CONFIG_PCI
170 #define CONFIG_NET_MULTI
171 #define CONFIG_PCI_SCAN_SHOW
172 #endif
173 #endif
174 
175 /* Command line configuration */
176 
177 /*  MMC  */
178 #ifndef SPL_NO_MMC
179 #ifdef CONFIG_MMC
180 #define CONFIG_FSL_ESDHC
181 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
182 #endif
183 #endif
184 
185 /*  DSPI  */
186 #ifndef SPL_NO_DSPI
187 #define CONFIG_FSL_DSPI
188 #ifdef CONFIG_FSL_DSPI
189 #define CONFIG_DM_SPI_FLASH
190 #define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
191 #define CONFIG_SPI_FLASH_SST		/* cs1 */
192 #define CONFIG_SPI_FLASH_EON		/* cs2 */
193 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
194 #define CONFIG_SF_DEFAULT_BUS		1
195 #define CONFIG_SF_DEFAULT_CS		0
196 #endif
197 #endif
198 #endif
199 
200 /* FMan ucode */
201 #ifndef SPL_NO_FMAN
202 #define CONFIG_SYS_DPAA_FMAN
203 #ifdef CONFIG_SYS_DPAA_FMAN
204 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
205 
206 #ifdef CONFIG_NAND_BOOT
207 /* Store Fman ucode at offeset 0x900000(72 blocks). */
208 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
209 #define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
210 #elif defined(CONFIG_SD_BOOT)
211 /*
212  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
213  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
214  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
215  */
216 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
217 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
218 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
219 #elif defined(CONFIG_QSPI_BOOT)
220 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
221 #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
222 #define CONFIG_ENV_SPI_BUS		0
223 #define CONFIG_ENV_SPI_CS		0
224 #define CONFIG_ENV_SPI_MAX_HZ		1000000
225 #define CONFIG_ENV_SPI_MODE		0x03
226 #else
227 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
228 /* FMan fireware Pre-load address */
229 #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
230 #define CONFIG_SYS_QE_FW_ADDR		0x60940000
231 #endif
232 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
233 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
234 #endif
235 #endif
236 
237 /* Miscellaneous configurable options */
238 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
239 
240 #define CONFIG_HWCONFIG
241 #define HWCONFIG_BUFFER_SIZE		128
242 
243 #ifndef SPL_NO_MISC
244 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
245 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
246 			"5m(kernel),1m(dtb),9m(file_system)"
247 #else
248 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
249 			"2m@0x100000(nor_bank0_uboot),"\
250 			"40m@0x1100000(nor_bank0_fit)," \
251 			"7m(nor_bank0_user)," \
252 			"2m@0x4100000(nor_bank4_uboot)," \
253 			"40m@0x5100000(nor_bank4_fit),"\
254 			"-(nor_bank4_user);" \
255 			"7e800000.flash:" \
256 			"1m(nand_uboot),1m(nand_uboot_env)," \
257 			"20m(nand_fit);spi0.0:1m(uboot)," \
258 			"5m(kernel),1m(dtb),9m(file_system)"
259 #endif
260 
261 #include <config_distro_defaults.h>
262 #ifndef CONFIG_SPL_BUILD
263 #define BOOT_TARGET_DEVICES(func) \
264 	func(MMC, mmc, 0) \
265 	func(USB, usb, 0)
266 #include <config_distro_bootcmd.h>
267 #endif
268 
269 /* Initial environment variables */
270 #define CONFIG_EXTRA_ENV_SETTINGS		\
271 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
272 	"fdt_high=0xffffffffffffffff\0"		\
273 	"initrd_high=0xffffffffffffffff\0"	\
274 	"fdt_addr=0x64f00000\0"		 	\
275 	"kernel_addr=0x65000000\0"		\
276 	"scriptaddr=0x80000000\0"		\
277 	"scripthdraddr=0x80080000\0"		\
278 	"fdtheader_addr_r=0x80100000\0"		\
279 	"kernelheader_addr_r=0x80200000\0"	\
280 	"kernel_addr_r=0x81000000\0"		\
281 	"fdt_addr_r=0x90000000\0"		\
282 	"load_addr=0xa0000000\0"		\
283 	"kernel_size=0x2800000\0"		\
284 	"console=ttyS0,115200\0"		\
285 	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
286 	BOOTENV					\
287 	"boot_scripts=ls1043ardb_boot.scr\0"	\
288 	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
289 	"scan_dev_for_boot_part="		\
290 		"part list ${devtype} ${devnum} devplist; "	\
291 		"env exists devplist || setenv devplist 1; "	\
292 		"for distro_bootpart in ${devplist}; do "	\
293 			"if fstype ${devtype} "			\
294 				"${devnum}:${distro_bootpart} "	\
295 				"bootfstype; then "		\
296 				"run scan_dev_for_boot; "	\
297 			"fi; "					\
298 		"done\0"			\
299 	"scan_dev_for_boot="					\
300 		"echo Scanning ${devtype} "			\
301 			"${devnum}:${distro_bootpart}...; "	\
302 		"for prefix in ${boot_prefixes}; do "		\
303 			"run scan_dev_for_scripts; "		\
304 		"done;\0"					\
305 	"boot_a_script="					\
306 		"load ${devtype} ${devnum}:${distro_bootpart} "	\
307 			"${scriptaddr} ${prefix}${script}; "	\
308 		"env exists secureboot && load ${devtype} "	\
309 			"${devnum}:${distro_bootpart} "		\
310 			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
311 			"&& esbc_validate ${scripthdraddr};"	\
312 		"source ${scriptaddr}\0"			\
313 	"installer=load mmc 0:2 $load_addr "	\
314 		"/flex_installer_arm64.itb; "	\
315 		"bootm $load_addr#ls1043ardb\0"	\
316 	"qspi_bootcmd=echo Trying load from qspi..;"	\
317 		"sf probe && sf read $load_addr "	\
318 		"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
319 	"nor_bootcmd=echo Trying load from nor..;"	\
320 		"cp.b $kernel_addr $load_addr "	\
321 		"$kernel_size && bootm $load_addr#$board\0"
322 
323 #undef CONFIG_BOOTCOMMAND
324 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
325 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
326 			   "&& esbc_halt; run qspi_bootcmd;"
327 #else
328 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
329 			   "&& esbc_halt; run nor_bootcmd;"
330 #endif
331 
332 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
333 					"earlycon=uart8250,mmio,0x21c0500 "    \
334 					MTDPARTS_DEFAULT
335 #endif
336 
337 /* Monitor Command Prompt */
338 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
339 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
340 					sizeof(CONFIG_SYS_PROMPT) + 16)
341 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
342 #define CONFIG_SYS_LONGHELP
343 
344 #ifndef SPL_NO_MISC
345 #ifndef CONFIG_CMDLINE_EDITING
346 #define CONFIG_CMDLINE_EDITING		1
347 #endif
348 #endif
349 
350 #define CONFIG_AUTO_COMPLETE
351 #define CONFIG_SYS_MAXARGS		64	/* max command args */
352 
353 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
354 
355 #include <asm/arch/soc.h>
356 
357 #endif /* __LS1043A_COMMON_H */
358