1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_FMAN 13 #define SPL_NO_DSPI 14 #define SPL_NO_PCIE 15 #define SPL_NO_ENV 16 #define SPL_NO_MISC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QE 20 #define SPL_NO_EEPROM 21 #endif 22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 23 #define SPL_NO_MMC 24 #endif 25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_FSL_LAYERSCAPE 31 #define CONFIG_LS1043A 32 #define CONFIG_MP 33 #define CONFIG_GICV2 34 35 #include <asm/arch/stream_id_lsch2.h> 36 #include <asm/arch/config.h> 37 38 /* Link Definitions */ 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 40 41 #define CONFIG_SUPPORT_RAW_INITRD 42 43 #define CONFIG_SKIP_LOWLEVEL_INIT 44 45 #define CONFIG_VERY_BIG_RAM 46 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 47 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 49 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 50 51 #define CPU_RELEASE_ADDR secondary_boot_func 52 53 /* Generic Timer Definitions */ 54 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 55 56 /* Size of malloc() pool */ 57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 58 59 /* Serial Port */ 60 #define CONFIG_CONS_INDEX 1 61 #define CONFIG_SYS_NS16550_SERIAL 62 #define CONFIG_SYS_NS16550_REG_SIZE 1 63 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 64 65 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 66 67 /* SD boot SPL */ 68 #ifdef CONFIG_SD_BOOT 69 #define CONFIG_SPL_FRAMEWORK 70 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 71 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 72 73 #define CONFIG_SPL_TEXT_BASE 0x10000000 74 #define CONFIG_SPL_MAX_SIZE 0x1d000 75 #define CONFIG_SPL_STACK 0x1001e000 76 #define CONFIG_SPL_PAD_TO 0x1d000 77 78 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 79 CONFIG_SYS_MONITOR_LEN) 80 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 81 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 83 #define CONFIG_SYS_MONITOR_LEN 0xa0000 84 #endif 85 86 /* NAND SPL */ 87 #ifdef CONFIG_NAND_BOOT 88 #define CONFIG_SPL_PBL_PAD 89 #define CONFIG_SPL_FRAMEWORK 90 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 91 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 92 #define CONFIG_SPL_TEXT_BASE 0x10000000 93 #define CONFIG_SPL_MAX_SIZE 0x1a000 94 #define CONFIG_SPL_STACK 0x1001d000 95 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 96 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 98 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 99 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 100 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 101 #define CONFIG_SYS_MONITOR_LEN 0xa0000 102 #endif 103 104 /* IFC */ 105 #ifndef SPL_NO_IFC 106 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 107 #define CONFIG_FSL_IFC 108 /* 109 * CONFIG_SYS_FLASH_BASE has the final address (core view) 110 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 111 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 112 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 113 */ 114 #define CONFIG_SYS_FLASH_BASE 0x60000000 115 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 116 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 117 118 #ifdef CONFIG_MTD_NOR_FLASH 119 #define CONFIG_FLASH_CFI_DRIVER 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 122 #define CONFIG_SYS_FLASH_QUIET_TEST 123 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 124 #endif 125 #endif 126 #endif 127 128 /* I2C */ 129 #define CONFIG_SYS_I2C 130 #define CONFIG_SYS_I2C_MXC 131 #define CONFIG_SYS_I2C_MXC_I2C1 132 #define CONFIG_SYS_I2C_MXC_I2C2 133 #define CONFIG_SYS_I2C_MXC_I2C3 134 #define CONFIG_SYS_I2C_MXC_I2C4 135 136 /* PCIe */ 137 #ifndef SPL_NO_PCIE 138 #define CONFIG_PCIE1 /* PCIE controller 1 */ 139 #define CONFIG_PCIE2 /* PCIE controller 2 */ 140 #define CONFIG_PCIE3 /* PCIE controller 3 */ 141 142 #ifdef CONFIG_PCI 143 #define CONFIG_NET_MULTI 144 #define CONFIG_PCI_SCAN_SHOW 145 #define CONFIG_CMD_PCI 146 #endif 147 #endif 148 149 /* Command line configuration */ 150 #ifndef SPL_NO_ENV 151 #define CONFIG_CMD_ENV 152 #endif 153 154 /* MMC */ 155 #ifndef SPL_NO_MMC 156 #ifdef CONFIG_MMC 157 #define CONFIG_FSL_ESDHC 158 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 159 #endif 160 #endif 161 162 /* DSPI */ 163 #ifndef SPL_NO_DSPI 164 #define CONFIG_FSL_DSPI 165 #ifdef CONFIG_FSL_DSPI 166 #define CONFIG_DM_SPI_FLASH 167 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 168 #define CONFIG_SPI_FLASH_SST /* cs1 */ 169 #define CONFIG_SPI_FLASH_EON /* cs2 */ 170 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 171 #define CONFIG_SF_DEFAULT_BUS 1 172 #define CONFIG_SF_DEFAULT_CS 0 173 #endif 174 #endif 175 #endif 176 177 /* FMan ucode */ 178 #ifndef SPL_NO_FMAN 179 #define CONFIG_SYS_DPAA_FMAN 180 #ifdef CONFIG_SYS_DPAA_FMAN 181 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 182 183 #ifdef CONFIG_NAND_BOOT 184 /* Store Fman ucode at offeset 0x160000(11 blocks). */ 185 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 186 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #elif defined(CONFIG_SD_BOOT) 188 /* 189 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 190 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 191 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). 192 */ 193 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 194 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 195 #elif defined(CONFIG_QSPI_BOOT) 196 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 197 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 198 #define CONFIG_ENV_SPI_BUS 0 199 #define CONFIG_ENV_SPI_CS 0 200 #define CONFIG_ENV_SPI_MAX_HZ 1000000 201 #define CONFIG_ENV_SPI_MODE 0x03 202 #else 203 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 204 /* FMan fireware Pre-load address */ 205 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 206 #endif 207 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 208 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 209 #endif 210 #endif 211 212 /* Miscellaneous configurable options */ 213 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 214 215 #define CONFIG_HWCONFIG 216 #define HWCONFIG_BUFFER_SIZE 128 217 218 #ifndef SPL_NO_MISC 219 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 220 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ 221 "5m(kernel),1m(dtb),9m(file_system)" 222 #else 223 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ 224 "2m@0x100000(nor_bank0_uboot),"\ 225 "40m@0x1100000(nor_bank0_fit)," \ 226 "7m(nor_bank0_user)," \ 227 "2m@0x4100000(nor_bank4_uboot)," \ 228 "40m@0x5100000(nor_bank4_fit),"\ 229 "-(nor_bank4_user);" \ 230 "7e800000.flash:" \ 231 "1m(nand_uboot),1m(nand_uboot_env)," \ 232 "20m(nand_fit);spi0.0:1m(uboot)," \ 233 "5m(kernel),1m(dtb),9m(file_system)" 234 #endif 235 236 /* Initial environment variables */ 237 #define CONFIG_EXTRA_ENV_SETTINGS \ 238 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 239 "loadaddr=0x80100000\0" \ 240 "fdt_high=0xffffffffffffffff\0" \ 241 "initrd_high=0xffffffffffffffff\0" \ 242 "kernel_start=0x61100000\0" \ 243 "kernel_load=0xa0000000\0" \ 244 "kernel_size=0x2800000\0" \ 245 "console=ttyS0,115200\0" \ 246 "mtdparts=" MTDPARTS_DEFAULT "\0" 247 248 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 249 "earlycon=uart8250,mmio,0x21c0500 " \ 250 MTDPARTS_DEFAULT 251 252 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 253 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ 254 "e0000 f00000 && bootm $kernel_load" 255 #else 256 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 257 "$kernel_size && bootm $kernel_load" 258 #endif 259 #endif 260 261 /* Monitor Command Prompt */ 262 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 263 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 264 sizeof(CONFIG_SYS_PROMPT) + 16) 265 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 266 #define CONFIG_SYS_LONGHELP 267 268 #ifndef SPL_NO_MISC 269 #define CONFIG_CMDLINE_EDITING 1 270 #endif 271 272 #define CONFIG_AUTO_COMPLETE 273 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 274 275 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 276 277 /* Hash command with SHA acceleration supported in hardware */ 278 #ifdef CONFIG_FSL_CAAM 279 #define CONFIG_CMD_HASH 280 #define CONFIG_SHA_HW_ACCEL 281 #endif 282 283 #endif /* __LS1043A_COMMON_H */ 284