1 /* 2 * Copyright (C) 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_FMAN 13 #define SPL_NO_DSPI 14 #define SPL_NO_PCIE 15 #define SPL_NO_ENV 16 #define SPL_NO_MISC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QE 20 #define SPL_NO_EEPROM 21 #endif 22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 23 #define SPL_NO_MMC 24 #endif 25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_FSL_LAYERSCAPE 31 #define CONFIG_MP 32 #define CONFIG_GICV2 33 34 #include <asm/arch/stream_id_lsch2.h> 35 #include <asm/arch/config.h> 36 37 /* Link Definitions */ 38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 39 40 #define CONFIG_SUPPORT_RAW_INITRD 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 49 50 #define CPU_RELEASE_ADDR secondary_boot_func 51 52 /* Generic Timer Definitions */ 53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 54 55 /* Size of malloc() pool */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 57 58 /* Serial Port */ 59 #define CONFIG_CONS_INDEX 1 60 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_REG_SIZE 1 62 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 63 64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 65 66 /* SD boot SPL */ 67 #ifdef CONFIG_SD_BOOT 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x17000 72 #define CONFIG_SPL_STACK 0x1001e000 73 #define CONFIG_SPL_PAD_TO 0x1d000 74 75 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 76 CONFIG_SPL_BSS_MAX_SIZE) 77 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 78 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 79 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 80 81 #ifdef CONFIG_SECURE_BOOT 82 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 83 /* 84 * HDR would be appended at end of image and copied to DDR along 85 * with U-Boot image. Here u-boot max. size is 512K. So if binary 86 * size increases then increase this size in case of secure boot as 87 * it uses raw u-boot image instead of fit image. 88 */ 89 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 90 #else 91 #define CONFIG_SYS_MONITOR_LEN 0x100000 92 #endif /* ifdef CONFIG_SECURE_BOOT */ 93 #endif 94 95 /* NAND SPL */ 96 #ifdef CONFIG_NAND_BOOT 97 #define CONFIG_SPL_PBL_PAD 98 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 99 #define CONFIG_SPL_TEXT_BASE 0x10000000 100 #define CONFIG_SPL_MAX_SIZE 0x1a000 101 #define CONFIG_SPL_STACK 0x1001d000 102 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 104 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 105 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 106 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 107 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 108 109 #ifdef CONFIG_SECURE_BOOT 110 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 111 #endif /* ifdef CONFIG_SECURE_BOOT */ 112 113 #ifdef CONFIG_U_BOOT_HDR_SIZE 114 /* 115 * HDR would be appended at end of image and copied to DDR along 116 * with U-Boot image. Here u-boot max. size is 512K. So if binary 117 * size increases then increase this size in case of secure boot as 118 * it uses raw u-boot image instead of fit image. 119 */ 120 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 121 #else 122 #define CONFIG_SYS_MONITOR_LEN 0x100000 123 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 124 125 #endif 126 127 /* IFC */ 128 #ifndef SPL_NO_IFC 129 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 130 #define CONFIG_FSL_IFC 131 /* 132 * CONFIG_SYS_FLASH_BASE has the final address (core view) 133 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 134 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 135 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 136 */ 137 #define CONFIG_SYS_FLASH_BASE 0x60000000 138 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 139 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 140 141 #ifdef CONFIG_MTD_NOR_FLASH 142 #define CONFIG_FLASH_CFI_DRIVER 143 #define CONFIG_SYS_FLASH_CFI 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 145 #define CONFIG_SYS_FLASH_QUIET_TEST 146 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 147 #endif 148 #endif 149 #endif 150 151 /* I2C */ 152 #define CONFIG_SYS_I2C 153 #define CONFIG_SYS_I2C_MXC 154 #define CONFIG_SYS_I2C_MXC_I2C1 155 #define CONFIG_SYS_I2C_MXC_I2C2 156 #define CONFIG_SYS_I2C_MXC_I2C3 157 #define CONFIG_SYS_I2C_MXC_I2C4 158 159 /* PCIe */ 160 #ifndef SPL_NO_PCIE 161 #define CONFIG_PCIE1 /* PCIE controller 1 */ 162 #define CONFIG_PCIE2 /* PCIE controller 2 */ 163 #define CONFIG_PCIE3 /* PCIE controller 3 */ 164 165 #ifdef CONFIG_PCI 166 #define CONFIG_PCI_SCAN_SHOW 167 #endif 168 #endif 169 170 /* Command line configuration */ 171 172 /* MMC */ 173 #ifndef SPL_NO_MMC 174 #ifdef CONFIG_MMC 175 #define CONFIG_FSL_ESDHC 176 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 177 #endif 178 #endif 179 180 /* DSPI */ 181 #ifndef SPL_NO_DSPI 182 #define CONFIG_FSL_DSPI 183 #ifdef CONFIG_FSL_DSPI 184 #define CONFIG_DM_SPI_FLASH 185 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 186 #define CONFIG_SPI_FLASH_SST /* cs1 */ 187 #define CONFIG_SPI_FLASH_EON /* cs2 */ 188 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 189 #define CONFIG_SF_DEFAULT_BUS 1 190 #define CONFIG_SF_DEFAULT_CS 0 191 #endif 192 #endif 193 #endif 194 195 /* FMan ucode */ 196 #ifndef SPL_NO_FMAN 197 #define CONFIG_SYS_DPAA_FMAN 198 #ifdef CONFIG_SYS_DPAA_FMAN 199 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 200 201 #ifdef CONFIG_NAND_BOOT 202 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 203 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 204 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 205 #elif defined(CONFIG_SD_BOOT) 206 /* 207 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 208 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 209 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 210 */ 211 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 212 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 213 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) 214 #elif defined(CONFIG_QSPI_BOOT) 215 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 216 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 217 #define CONFIG_ENV_SPI_BUS 0 218 #define CONFIG_ENV_SPI_CS 0 219 #define CONFIG_ENV_SPI_MAX_HZ 1000000 220 #define CONFIG_ENV_SPI_MODE 0x03 221 #else 222 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 223 /* FMan fireware Pre-load address */ 224 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 225 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 226 #endif 227 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 228 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 229 #endif 230 #endif 231 232 /* Miscellaneous configurable options */ 233 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 234 235 #define CONFIG_HWCONFIG 236 #define HWCONFIG_BUFFER_SIZE 128 237 238 #ifndef SPL_NO_MISC 239 #include <config_distro_defaults.h> 240 #ifndef CONFIG_SPL_BUILD 241 #define BOOT_TARGET_DEVICES(func) \ 242 func(MMC, mmc, 0) \ 243 func(USB, usb, 0) 244 #include <config_distro_bootcmd.h> 245 #endif 246 247 /* Initial environment variables */ 248 #define CONFIG_EXTRA_ENV_SETTINGS \ 249 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 250 "fdt_high=0xffffffffffffffff\0" \ 251 "initrd_high=0xffffffffffffffff\0" \ 252 "fdt_addr=0x64f00000\0" \ 253 "kernel_addr=0x61000000\0" \ 254 "scriptaddr=0x80000000\0" \ 255 "scripthdraddr=0x80080000\0" \ 256 "fdtheader_addr_r=0x80100000\0" \ 257 "kernelheader_addr_r=0x80200000\0" \ 258 "kernel_addr_r=0x81000000\0" \ 259 "fdt_addr_r=0x90000000\0" \ 260 "load_addr=0xa0000000\0" \ 261 "kernelheader_addr=0x60800000\0" \ 262 "kernel_size=0x2800000\0" \ 263 "kernelheader_size=0x40000\0" \ 264 "kernel_addr_sd=0x8000\0" \ 265 "kernel_size_sd=0x14000\0" \ 266 "kernelhdr_addr_sd=0x4000\0" \ 267 "kernelhdr_size_sd=0x10\0" \ 268 "console=ttyS0,115200\0" \ 269 "boot_os=y\0" \ 270 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 271 BOOTENV \ 272 "boot_scripts=ls1043ardb_boot.scr\0" \ 273 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 274 "scan_dev_for_boot_part=" \ 275 "part list ${devtype} ${devnum} devplist; " \ 276 "env exists devplist || setenv devplist 1; " \ 277 "for distro_bootpart in ${devplist}; do " \ 278 "if fstype ${devtype} " \ 279 "${devnum}:${distro_bootpart} " \ 280 "bootfstype; then " \ 281 "run scan_dev_for_boot; " \ 282 "fi; " \ 283 "done\0" \ 284 "scan_dev_for_boot=" \ 285 "echo Scanning ${devtype} " \ 286 "${devnum}:${distro_bootpart}...; " \ 287 "for prefix in ${boot_prefixes}; do " \ 288 "run scan_dev_for_scripts; " \ 289 "done;\0" \ 290 "boot_a_script=" \ 291 "load ${devtype} ${devnum}:${distro_bootpart} " \ 292 "${scriptaddr} ${prefix}${script}; " \ 293 "env exists secureboot && load ${devtype} " \ 294 "${devnum}:${distro_bootpart} " \ 295 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 296 "&& esbc_validate ${scripthdraddr};" \ 297 "source ${scriptaddr}\0" \ 298 "qspi_bootcmd=echo Trying load from qspi..;" \ 299 "sf probe && sf read $load_addr " \ 300 "$kernel_addr $kernel_size; env exists secureboot " \ 301 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 302 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 303 "bootm $load_addr#$board\0" \ 304 "nor_bootcmd=echo Trying load from nor..;" \ 305 "cp.b $kernel_addr $load_addr " \ 306 "$kernel_size; env exists secureboot " \ 307 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 308 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 309 "bootm $load_addr#$board\0" \ 310 "sd_bootcmd=echo Trying load from SD ..;" \ 311 "mmcinfo; mmc read $load_addr " \ 312 "$kernel_addr_sd $kernel_size_sd && " \ 313 "env exists secureboot && mmc read $kernelheader_addr_r " \ 314 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 315 " && esbc_validate ${kernelheader_addr_r};" \ 316 "bootm $load_addr#$board\0" 317 318 319 #undef CONFIG_BOOTCOMMAND 320 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 321 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 322 "env exists secureboot && esbc_halt;" 323 #elif defined(CONFIG_SD_BOOT) 324 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 325 "env exists secureboot && esbc_halt;" 326 #else 327 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 328 "env exists secureboot && esbc_halt;" 329 #endif 330 #endif 331 332 /* Monitor Command Prompt */ 333 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 334 #define CONFIG_SYS_LONGHELP 335 336 #ifndef SPL_NO_MISC 337 #ifndef CONFIG_CMDLINE_EDITING 338 #define CONFIG_CMDLINE_EDITING 1 339 #endif 340 #endif 341 342 #define CONFIG_AUTO_COMPLETE 343 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 344 345 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 346 347 #include <asm/arch/soc.h> 348 349 #endif /* __LS1043A_COMMON_H */ 350