1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #define CONFIG_SYS_CLK_FREQ 100000000 36 #define CONFIG_DDR_CLK_FREQ 100000000 37 38 #ifdef CONFIG_RAMBOOT_PBL 39 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 40 #endif 41 42 #ifdef CONFIG_SD_BOOT 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg 44 #define CONFIG_SPL_FRAMEWORK 45 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 46 #define CONFIG_SPL_LIBCOMMON_SUPPORT 47 #define CONFIG_SPL_LIBGENERIC_SUPPORT 48 #define CONFIG_SPL_ENV_SUPPORT 49 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 50 #define CONFIG_SPL_I2C_SUPPORT 51 #define CONFIG_SPL_WATCHDOG_SUPPORT 52 #define CONFIG_SPL_SERIAL_SUPPORT 53 #define CONFIG_SPL_MMC_SUPPORT 54 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 55 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 56 57 #define CONFIG_SPL_TEXT_BASE 0x10000000 58 #define CONFIG_SPL_MAX_SIZE 0x1a000 59 #define CONFIG_SPL_STACK 0x1001d000 60 #define CONFIG_SPL_PAD_TO 0x1c000 61 #define CONFIG_SYS_TEXT_BASE 0x82000000 62 63 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 64 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 65 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 66 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 67 #define CONFIG_SYS_MONITOR_LEN 0x80000 68 #endif 69 70 #ifdef CONFIG_QSPI_BOOT 71 #define CONFIG_SYS_TEXT_BASE 0x40010000 72 #define CONFIG_SYS_NO_FLASH 73 #endif 74 75 #ifndef CONFIG_SYS_TEXT_BASE 76 #define CONFIG_SYS_TEXT_BASE 0x67f80000 77 #endif 78 79 #define CONFIG_NR_DRAM_BANKS 1 80 #define PHYS_SDRAM 0x80000000 81 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 82 83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 85 86 #define CONFIG_SYS_HAS_SERDES 87 88 #define CONFIG_FSL_CAAM /* Enable CAAM */ 89 90 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 91 !defined(CONFIG_QSPI_BOOT) 92 #define CONFIG_U_QE 93 #endif 94 95 /* 96 * IFC Definitions 97 */ 98 #ifndef CONFIG_QSPI_BOOT 99 #define CONFIG_FSL_IFC 100 #define CONFIG_SYS_FLASH_BASE 0x60000000 101 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 102 103 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 104 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 105 CSPR_PORT_SIZE_16 | \ 106 CSPR_MSEL_NOR | \ 107 CSPR_V) 108 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 109 110 /* NOR Flash Timing Params */ 111 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 112 CSOR_NOR_TRHZ_80) 113 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 114 FTIM0_NOR_TEADC(0x5) | \ 115 FTIM0_NOR_TAVDS(0x0) | \ 116 FTIM0_NOR_TEAHC(0x5)) 117 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 118 FTIM1_NOR_TRAD_NOR(0x1A) | \ 119 FTIM1_NOR_TSEQRAD_NOR(0x13)) 120 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 121 FTIM2_NOR_TCH(0x4) | \ 122 FTIM2_NOR_TWP(0x1c) | \ 123 FTIM2_NOR_TWPH(0x0e)) 124 #define CONFIG_SYS_NOR_FTIM3 0 125 126 #define CONFIG_FLASH_CFI_DRIVER 127 #define CONFIG_SYS_FLASH_CFI 128 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 129 #define CONFIG_SYS_FLASH_QUIET_TEST 130 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 131 132 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 133 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 136 137 #define CONFIG_SYS_FLASH_EMPTY_INFO 138 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 139 140 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 141 #define CONFIG_SYS_WRITE_SWAPPED_DATA 142 #endif 143 144 /* CPLD */ 145 146 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 147 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 148 149 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 150 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 151 CSPR_PORT_SIZE_8 | \ 152 CSPR_MSEL_GPCM | \ 153 CSPR_V) 154 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 155 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 156 CSOR_NOR_NOR_MODE_AVD_NOR | \ 157 CSOR_NOR_TRHZ_80) 158 159 /* CPLD Timing parameters for IFC GPCM */ 160 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 161 FTIM0_GPCM_TEADC(0xf) | \ 162 FTIM0_GPCM_TEAHC(0xf)) 163 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 164 FTIM1_GPCM_TRAD(0x3f)) 165 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 166 FTIM2_GPCM_TCH(0xf) | \ 167 FTIM2_GPCM_TWP(0xff)) 168 #define CONFIG_SYS_FPGA_FTIM3 0x0 169 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 170 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 171 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 172 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 173 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 174 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 175 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 176 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 177 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 178 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 179 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 180 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 181 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 182 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 183 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 184 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 185 186 /* 187 * Serial Port 188 */ 189 #ifdef CONFIG_LPUART 190 #define CONFIG_FSL_LPUART 191 #define CONFIG_LPUART_32B_REG 192 #else 193 #define CONFIG_CONS_INDEX 1 194 #define CONFIG_SYS_NS16550 195 #define CONFIG_SYS_NS16550_SERIAL 196 #define CONFIG_SYS_NS16550_REG_SIZE 1 197 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 198 #endif 199 200 #define CONFIG_BAUDRATE 115200 201 202 /* 203 * I2C 204 */ 205 #define CONFIG_CMD_I2C 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_MXC 208 209 /* EEPROM */ 210 #ifndef CONFIG_SD_BOOT 211 #define CONFIG_ID_EEPROM 212 #define CONFIG_SYS_I2C_EEPROM_NXID 213 #define CONFIG_SYS_EEPROM_BUS_NUM 1 214 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 218 #endif 219 220 /* 221 * MMC 222 */ 223 #define CONFIG_MMC 224 #define CONFIG_CMD_MMC 225 #define CONFIG_FSL_ESDHC 226 #define CONFIG_GENERIC_MMC 227 228 #define CONFIG_CMD_FAT 229 #define CONFIG_DOS_PARTITION 230 231 /* QSPI */ 232 #ifdef CONFIG_QSPI_BOOT 233 #define CONFIG_FSL_QSPI 234 #define QSPI0_AMBA_BASE 0x40000000 235 #define FSL_QSPI_FLASH_SIZE (1 << 24) 236 #define FSL_QSPI_FLASH_NUM 2 237 238 #define CONFIG_CMD_SF 239 #define CONFIG_SPI_FLASH 240 #define CONFIG_SPI_FLASH_STMICRO 241 #endif 242 243 /* 244 * Video 245 */ 246 #define CONFIG_FSL_DCU_FB 247 248 #ifdef CONFIG_FSL_DCU_FB 249 #define CONFIG_VIDEO 250 #define CONFIG_CMD_BMP 251 #define CONFIG_CFB_CONSOLE 252 #define CONFIG_VGA_AS_SINGLE_DEVICE 253 #define CONFIG_VIDEO_LOGO 254 #define CONFIG_VIDEO_BMP_LOGO 255 256 #define CONFIG_FSL_DCU_SII9022A 257 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 258 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 259 #endif 260 261 /* 262 * eTSEC 263 */ 264 #define CONFIG_TSEC_ENET 265 266 #ifdef CONFIG_TSEC_ENET 267 #define CONFIG_MII 268 #define CONFIG_MII_DEFAULT_TSEC 1 269 #define CONFIG_TSEC1 1 270 #define CONFIG_TSEC1_NAME "eTSEC1" 271 #define CONFIG_TSEC2 1 272 #define CONFIG_TSEC2_NAME "eTSEC2" 273 #define CONFIG_TSEC3 1 274 #define CONFIG_TSEC3_NAME "eTSEC3" 275 276 #define TSEC1_PHY_ADDR 2 277 #define TSEC2_PHY_ADDR 0 278 #define TSEC3_PHY_ADDR 1 279 280 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 281 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 282 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 283 284 #define TSEC1_PHYIDX 0 285 #define TSEC2_PHYIDX 0 286 #define TSEC3_PHYIDX 0 287 288 #define CONFIG_ETHPRIME "eTSEC1" 289 290 #define CONFIG_PHY_GIGE 291 #define CONFIG_PHYLIB 292 #define CONFIG_PHY_ATHEROS 293 294 #define CONFIG_HAS_ETH0 295 #define CONFIG_HAS_ETH1 296 #define CONFIG_HAS_ETH2 297 #endif 298 299 /* PCIe */ 300 #define CONFIG_PCI /* Enable PCI/PCIE */ 301 #define CONFIG_PCIE1 /* PCIE controler 1 */ 302 #define CONFIG_PCIE2 /* PCIE controler 2 */ 303 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 304 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 305 306 #define CONFIG_SYS_PCI_64BIT 307 308 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 309 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 310 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 311 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 312 313 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 314 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 315 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 316 317 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 318 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 319 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 320 321 #ifdef CONFIG_PCI 322 #define CONFIG_NET_MULTI 323 #define CONFIG_PCI_PNP 324 #define CONFIG_E1000 325 #define CONFIG_PCI_SCAN_SHOW 326 #define CONFIG_CMD_PCI 327 #define CONFIG_CMD_NET 328 #endif 329 330 #define CONFIG_CMD_PING 331 #define CONFIG_CMD_DHCP 332 #define CONFIG_CMD_MII 333 #define CONFIG_CMD_NET 334 335 #define CONFIG_CMDLINE_TAG 336 #define CONFIG_CMDLINE_EDITING 337 338 #ifdef CONFIG_QSPI_BOOT 339 #undef CONFIG_CMD_IMLS 340 #else 341 #define CONFIG_CMD_IMLS 342 #endif 343 344 #define CONFIG_ARMV7_NONSEC 345 #define CONFIG_ARMV7_VIRT 346 #define CONFIG_PEN_ADDR_BIG_ENDIAN 347 #define CONFIG_LS102XA_NS_ACCESS 348 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 349 #define CONFIG_TIMER_CLK_FREQ 12500000 350 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 351 352 #define CONFIG_HWCONFIG 353 #define HWCONFIG_BUFFER_SIZE 128 354 355 #define CONFIG_BOOTDELAY 3 356 357 #ifdef CONFIG_LPUART 358 #define CONFIG_EXTRA_ENV_SETTINGS \ 359 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 360 "initrd_high=0xcfffffff\0" \ 361 "fdt_high=0xcfffffff\0" 362 #else 363 #define CONFIG_EXTRA_ENV_SETTINGS \ 364 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 365 "initrd_high=0xcfffffff\0" \ 366 "fdt_high=0xcfffffff\0" 367 #endif 368 369 /* 370 * Miscellaneous configurable options 371 */ 372 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 373 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 374 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 375 #define CONFIG_AUTO_COMPLETE 376 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 377 #define CONFIG_SYS_PBSIZE \ 378 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 379 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 380 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 381 382 #define CONFIG_CMD_ENV_EXISTS 383 #define CONFIG_CMD_GREPENV 384 #define CONFIG_CMD_MEMINFO 385 #define CONFIG_CMD_MEMTEST 386 #define CONFIG_SYS_MEMTEST_START 0x80000000 387 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 388 389 #define CONFIG_SYS_LOAD_ADDR 0x82000000 390 391 #define CONFIG_LS102XA_STREAM_ID 392 393 /* 394 * Stack sizes 395 * The stack sizes are set up in start.S using the settings below 396 */ 397 #define CONFIG_STACKSIZE (30 * 1024) 398 399 #define CONFIG_SYS_INIT_SP_OFFSET \ 400 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 401 #define CONFIG_SYS_INIT_SP_ADDR \ 402 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 403 404 #ifdef CONFIG_SPL_BUILD 405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 406 #else 407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 408 #endif 409 410 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 411 412 /* 413 * Environment 414 */ 415 #define CONFIG_ENV_OVERWRITE 416 417 #if defined(CONFIG_SD_BOOT) 418 #define CONFIG_ENV_OFFSET 0x100000 419 #define CONFIG_ENV_IS_IN_MMC 420 #define CONFIG_SYS_MMC_ENV_DEV 0 421 #define CONFIG_ENV_SIZE 0x20000 422 #elif defined(CONFIG_QSPI_BOOT) 423 #define CONFIG_ENV_IS_IN_SPI_FLASH 424 #define CONFIG_ENV_SIZE 0x2000 425 #define CONFIG_ENV_OFFSET 0x100000 426 #define CONFIG_ENV_SECT_SIZE 0x10000 427 #else 428 #define CONFIG_ENV_IS_IN_FLASH 429 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 430 #define CONFIG_ENV_SIZE 0x20000 431 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 432 #endif 433 434 #define CONFIG_OF_LIBFDT 435 #define CONFIG_OF_BOARD_SETUP 436 #define CONFIG_CMD_BOOTZ 437 438 #define CONFIG_MISC_INIT_R 439 440 /* Hash command with SHA acceleration supported in hardware */ 441 #define CONFIG_CMD_HASH 442 #define CONFIG_SHA_HW_ACCEL 443 444 #ifdef CONFIG_SECURE_BOOT 445 #define CONFIG_CMD_BLOB 446 #endif 447 448 #endif 449